Revision 2.0 3.Signals and Protocol Specification 3.1 Pin Description A.G.P.protocol defines 20 new signals beyond what PCI uses.Which of these signals are implemented depends on which features of the bus are supported and whether the device is an A.G.P.master or target.The corelogic is required to support all signals required to: 1.Allow the A.G.P.master to enqueue requests and 2.Transfer data at 1x or 2x. The corelogic may optionally support: 1.Data transfers at 4x or 2.Fast Write(FW)transactions to the A.G.P.master. The A.G.P.master may optionally choose: 1.How it enqueues requests or 2.The rate at which it transfers data or 3.If it supports FW transactions. The A.G.P.signals follow the signal type definitions and naming convention used in the PCI Local Bus Specification.The following signal type definitions are from the view point of the A.G.P.target: in Input is an input-only signal. out Totem Pole Output is an active driver. t/s Tri-State is a bidirectional,tri-state input/output pin. s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time.The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float.A new agent cannot start driving an s/t/s signal any sooner than one clock after the previous agent tri- states it.A pull-up is required to sustain the inactive state until another agent drives it,and must be provided by the central resource(A.G.P.target or motherboard). The following tables list the signal names in the first column,signal types in the second column,and the signal descriptions in the third column.In the second column,the direction of a t/s or s/t/s signal is from the view point of the corelogic and is represented in the parentheses.For example,PIPE#is a sustained tri-state signal(s/t/s)that is always an input for the corelogic.The following tables describe the operation and use of each signal and are organized in four groups:A.G.P.Requests,A.G.P.Flow Control,A.G.P.Status,and A.G.P.Clocking. 31
Revision 2.0 31 3.1 Pin Description A.G.P. protocol defines 20 new signals beyond what PCI uses. Which of these signals are implemented depends on which features of the bus are supported and whether the device is an A.G.P. master or target. The corelogic is required to support all signals required to: 1. Allow the A.G.P. master to enqueue requests and 2. Transfer data at 1x or 2x. The corelogic may optionally support: 1. Data transfers at 4x or 2. Fast Write (FW) transactions to the A.G.P. master. The A.G.P. master may optionally choose: 1. How it enqueues requests or 2. The rate at which it transfers data or 3. If it supports FW transactions. The A.G.P. signals follow the signal type definitions and naming convention used in the PCI Local Bus Specification. The following signal type definitions are from the view point of the A.G.P. target: in Input is an input-only signal. out Totem Pole Output is an active driver. t/s Tri-State is a bidirectional, tri-state input/output pin. s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an s/t/s signal any sooner than one clock after the previous agent tristates it. A pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource (A.G.P. target or motherboard). The following tables list the signal names in the first column, signal types in the second column, and the signal descriptions in the third column. In the second column, the direction of a t/s or s/t/s signal is from the view point of the corelogic and is represented in the parentheses. For example, PIPE# is a sustained tri-state signal (s/t/s) that is always an input for the corelogic. The following tables describe the operation and use of each signal and are organized in four groups: A.G.P. Requests, A.G.P. Flow Control, A.G.P. Status, and A.G.P. Clocking. 3. Signals and Protocol Specification
Revision 2.0 Table 3-1:A.G.P.Requests Name Type Description PIPE# s/t/s Pipelined request is asserted by the current master to indicate a full width (in) request is to be enqueued by the target.The master enqueues one request each rising edge of CLK while PIPE#is asserted.When PIPE#is deasserted,no new requests are enqueued across the AD bus. PIPE#is a sustained tri-state signal from a master(graphics controller)and is an input to the target (the corelogic). SBA[7::0] in SideBand Address port provides an additional bus to pass requests (address and command)to the target from the master.SBA[7::0]are outputs from the master and an input to the target.This port is ignored by the target until enabled (see Section 6.1.10). Table 3-1 contains two mechanisms to enqueue requests by the A.G.P.master.The master chooses one mechanism at design time or during the initialization process and is not allowed to change during runtime.When PIPE#is used to enqueue requests,the master is not allowed to enqueue requests using the SBA port.When the SBA port is used to enqueue requests,PIPE#cannot be used to enqueue requests. Table 3-2:A.G.P.Flow Control Name Type Description RBF# n Read Buffer Full indicates if the master is ready to accept previously requested low priority read data or not.When RBF#is asserted,the arbiter is not allowed to initiate the return of low priority read data to the master. This signal must be pulled up by the central resource(A.G.P.target or motherboard). WBF# in Write Buffer Full indicates if the master is ready to accept FW data from the corelogic or not.When WBF#is asserted,the corelogic arbiter is not allowed to initiate a transaction to provide FW data.This signal must be pulled up by the central resource(A.G.P.target or motherboard). Table 3-2 contains the A.G.P.flow control beyond normal PCI flow control already required.When the master is always ready to accept the return of LP (Low Priority)Read data,the A.G.P.master is not required to implement RBF#and the corresponding pin on the target is tied(pulled up)in the deasserted state by the central resource. When the master is always ready to accept the first block of FW data,the A.G.P.master is not required to implement WBF#and the corresponding pin on the target is tied(pulled up)in the deasserted state by the central resource. Fast Write data is typically data generated by the CPU and pushed to the A.G.P.master.Refer to Section3.5.3.5 for details. 32
Revision 2.0 32 Table 3-1: A.G.P. Requests Name Type Description PIPE# s/t/s (in) Pipelined request is asserted by the current master to indicate a full width request is to be enqueued by the target. The master enqueues one request each rising edge of CLK while PIPE# is asserted. When PIPE# is deasserted, no new requests are enqueued across the AD bus. PIPE# is a sustained tri-state signal from a master (graphics controller) and is an input to the target (the corelogic). SBA[7::0] in SideBand Address port provides an additional bus to pass requests (address and command) to the target from the master. SBA[7::0] are outputs from the master and an input to the target. This port is ignored by the target until enabled (see Section 6.1.10). Table 3-1 contains two mechanisms to enqueue requests by the A.G.P. master. The master chooses one mechanism at design time or during the initialization process and is not allowed to change during runtime. When PIPE# is used to enqueue requests, the master is not allowed to enqueue requests using the SBA port. When the SBA port is used to enqueue requests, PIPE# cannot be used to enqueue requests. Table 3-2: A.G.P. Flow Control Name Type Description RBF# in Read Buffer Full indicates if the master is ready to accept previously requested low priority read data or not. When RBF# is asserted, the arbiter is not allowed to initiate the return of low priority read data to the master. This signal must be pulled up by the central resource (A.G.P. target or motherboard). WBF# in Write Buffer Full indicates if the master is ready to accept FW6 data from the corelogic or not. When WBF# is asserted, the corelogic arbiter is not allowed to initiate a transaction to provide FW data. This signal must be pulled up by the central resource (A.G.P. target or motherboard). Table 3-2 contains the A.G.P. flow control beyond normal PCI flow control already required. When the master is always ready to accept the return of LP (Low Priority) Read data, the A.G.P. master is not required to implement RBF# and the corresponding pin on the target is tied (pulled up) in the deasserted state by the central resource. When the master is always ready to accept the first block of FW data, the A.G.P. master is not required to implement WBF# and the corresponding pin on the target is tied (pulled up) in the deasserted state by the central resource. 6 Fast Write data is typically data generated by the CPU and pushed to the A.G.P. master. Refer to Section 3.5.3.5 for details
Revision 2.0 Table 3-3:A.G.P.Status Signals Name Type Description ST[2:0] out Status bus provides information from the arbiter to the master on what it may do.ST[2::0]only have meaning to the master when its GNT#is asserted. When GNT#is deasserted,these signals have no meaning and must be ignored. 000 Indicates that previously requested low priority read or flush data is being returned to the master. 001 Indicates that previously requested high priority read data is being returned to the master. 010 Indicates that the master is to provide low priority write data for a previous enqueued write command. 011 Indicates that the master is to provide high priority write data for a previous enqueued write command. 100 Reserved(Arbiter must not issue.May be defined in the future by Intel.) 101 Reserved(Arbiter must not issue.May be defined in the future by Intel.) 110 Reserved(Arbiter must not issue.May be defined in the future by Intel.) 111 Indicates that the master has been given permission to start a bus transaction.The master may enqueue A.G.P.Requests by asserting PIPE#or start a PCI transaction by asserting FRAME#.ST[2::0]are always an output from the corelogic and an input to the master. Table 3-3 describes the status signals,which indicate how the AD bus will be used for subsequent transactions.The AD bus can be used to enqueue new requests,return previously requested read data,or send previously enqueued write data.The ST[2::0]signals are qualified by the assertion of GNT#. 33
Revision 2.0 33 Table 3-3: A.G.P. Status Signals Name Type Description ST[2::0] out Status bus provides information from the arbiter to the master on what it may do. ST[2::0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted, these signals have no meaning and must be ignored. 000 Indicates that previously requested low priority read or flush data is being returned to the master. 001 Indicates that previously requested high priority read data is being returned to the master. 010 Indicates that the master is to provide low priority write data for a previous enqueued write command. 011 Indicates that the master is to provide high priority write data for a previous enqueued write command. 100 Reserved (Arbiter must not issue. May be defined in the future by Intel.) 101 Reserved (Arbiter must not issue. May be defined in the future by Intel.) 110 Reserved (Arbiter must not issue. May be defined in the future by Intel.) 111 Indicates that the master has been given permission to start a bus transaction. The master may enqueue A.G.P. Requests by asserting PIPE# or start a PCI transaction by asserting FRAME#. ST[2::0] are always an output from the corelogic and an input to the master. Table 3-3 describes the status signals, which indicate how the AD bus will be used for subsequent transactions. The AD bus can be used to enqueue new requests, return previously requested read data, or send previously enqueued write data. The ST[2::0] signals are qualified by the assertion of GNT#
Revision 2.0 Table 3-4:A.G.P.Clock List Name Type Description AD STBO s/t/s AD Bus Strobe 0 provides timing for 2x data transfer mode on AD[15::00]. (in/out) The agent that is providing data drives this signal. AD_STBO# slt/s AD Bus Strobe 0 compliment and AD_STBO provide timing for 4x data (in/out) transfer mode on AD[15::00].The agent that is providing data drives this signal. AD_STB1 s/t/s AD Bus Strobe 1 provides timing for 2x data transfer mode on AD[31::16]. (in/out) The agent that is providing data drives this signal. AD_STB1# s/t/s AD Bus Strobe 1 compliment and AD_STB1 provide timing for 4x data (in/out) transfer mode on AD[31:16].The agent that is providing data drives this signal. SB_STB s/t/s SideBand Strobe provides timing for SBA[7::0](when supported)and is (in) always driven by the A.G.P.master.When the SideBand Strobes have been idle,a synch cycle needs to be performed before a request can be enqueued.(See Section 4.1.2.10 for details). SB_STB# s/t/s SideBand Strobe compliment and SB_STB#provide timing for SBA[7::0] (in) (when supported)when 4x timing is supported and is always driven by the A.G.P.master. CLK t/s Clock provides timing for A.G.P.and PCI control signals. (out) Table 3-4 describes the clock signals used on the A.G.P.interface and when they are used.The basic CLK signal is used to time all control signals on the interface and is also used to transfer data in the Ix mode.The other two strobes are used to transfer data on the AD bus or the SBA port.Since the AD bus is 32 bits wide,two copies of the AD_STB are required.When the 4x mode is used,the compliments of the strobes are also required. The strobes basically follow the s/t/s definition,where the agent that asserts the signal is required to deassert it before tri-stating it.However,when ownership of the strobe changes,which occurs during a turn-around cycle,there is a period of time when both agents actively drive the strobe in the deasserted state.This condition occurs when one agent is returning the strobe to the deasserted state(finishing a transaction)while the other is preparing to actively assert the signal (starting a transaction).No contention occurs because the subsequent agent is not allowed to actively assert the strobe until after the time in which the first agent is required to have tri-stated the strobe.Refer to Section 4.2.2.2(2x)and Section 4.2.2.3(4x)for timing details. 34
Revision 2.0 34 Table 3-4: A.G.P. Clock List Name Type Description AD_STB0 s/t/s (in/out) AD Bus Strobe 0 provides timing for 2x data transfer mode on AD[15::00]. The agent that is providing data drives this signal. AD_STB0# s/t/s (in/out) AD Bus Strobe 0 compliment and AD_STB0 provide timing for 4x data transfer mode on AD[15::00]. The agent that is providing data drives this signal. AD_STB1 s/t/s (in/out) AD Bus Strobe 1 provides timing for 2x data transfer mode on AD[31::16]. The agent that is providing data drives this signal. AD_STB1# s/t/s (in/out) AD Bus Strobe 1 compliment and AD_STB1 provide timing for 4x data transfer mode on AD[31::16]. The agent that is providing data drives this signal. SB_STB s/t/s (in) SideBand Strobe provides timing for SBA[7::0] (when supported) and is always driven by the A.G.P. master. When the SideBand Strobes have been idle, a synch cycle needs to be performed before a request can be enqueued. (See Section 4.1.2.10 for details). SB_STB# s/t/s (in) SideBand Strobe compliment and SB_STB# provide timing for SBA[7::0] (when supported) when 4x timing is supported and is always driven by the A.G.P. master. CLK t/s (out) Clock provides timing for A.G.P. and PCI control signals. Table 3-4 describes the clock signals used on the A.G.P. interface and when they are used. The basic CLK signal is used to time all control signals on the interface and is also used to transfer data in the 1x mode. The other two strobes are used to transfer data on the AD bus or the SBA port. Since the AD bus is 32 bits wide, two copies of the AD_STB are required. When the 4x mode is used, the compliments of the strobes are also required. The strobes basically follow the s/t/s definition, where the agent that asserts the signal is required to deassert it before tri-stating it. However, when ownership of the strobe changes, which occurs during a turn-around cycle, there is a period of time when both agents actively drive the strobe in the deasserted state. This condition occurs when one agent is returning the strobe to the deasserted state (finishing a transaction) while the other is preparing to actively assert the signal (starting a transaction). No contention occurs because the subsequent agent is not allowed to actively assert the strobe until after the time in which the first agent is required to have tri-stated the strobe. Refer to Section 4.2.2.2 (2x) and Section 4.2.2.3 (4x) for timing details
Revision 2.0 Table 3-5:USB Signals Name Type Description USB+ t/s USB Positive Differential Data Line.used to send USB data and control packets to external peripheral devices(typically a USB capable video monitor in this application).For complete details on the USB signaling characteristics and requirements,see the Universal Serial Bus Specification. USB- t/s USB Negative Differential Data Line.See above reference. OVRCNT# Note 1 USB Overcurrent Indicator is low when too much current has been taken from the 5 volt power supply (Vbus)line on the monitor connector. Otherwise,the line is between 2.4 volts and Vddq. Notes 1. Overcurrent indication can be provided either by an active sense circuit or by a passive sensing of the USB power out (Vbus)after a fuse.An example of such a passive sensing circuit is a resistor divider of 10 K+5% from Vbus to OVRCNT#and 15 K+5%from OVRCNT#to ground.Implementations may vary.Boards which do not provide power to the monitor cable must pull this line to Vddq through a pull-up resistor. Table 3-5 is included in this specification to point out the USB signals that might be need by the graphics add-in card. Table 3-6:Power Management on A.G.P. Name Description PME# Power Management Event is not used by the A.G.P protocol,but is used by the PCI target interface when being power managed by the operating system. Refer to the PCI Bus Power Management Interface Specification for the definition of PME#and how a device is power managed by the operating system. Table 3-6 is included in this interface specification to point out the PCI Power Management signal which is used to control the power used by the device.Since an A.G.P.device is also a PCI target,the device follows the PCI Bus Power Management Interface Specification when supporting power management.Care needs to be taken when supporting power management to ensure correct operation and compliance with the power management specification. Table 3-7:Special Interface Signals Name Description TYPEDET# Type detect indicates whether the interface is 1.5 volt or 3.3 volt.Refer to Section 4.3.4 for a description of this signal. 35
Revision 2.0 35 Table 3-5: USB Signals Name Type Description USB+ t/s USB Positive Differential Data Line, used to send USB data and control packets to external peripheral devices (typically a USB capable video monitor in this application). For complete details on the USB signaling characteristics and requirements, see the Universal Serial Bus Specification. USB- t/s USB Negative Differential Data Line. See above reference. OVRCNT# Note 1 USB Overcurrent Indicator is low when too much current has been taken from the 5 volt power supply (Vbus) line on the monitor connector. Otherwise, the line is between 2.4 volts and Vddq. Notes 1. Overcurrent indication can be provided either by an active sense circuit or by a passive sensing of the USB power out (Vbus) after a fuse. An example of such a passive sensing circuit is a resistor divider of 10 KΩ ±5% from Vbus to OVRCNT# and 15 KΩ ±5% from OVRCNT# to ground. Implementations may vary. Boards which do not provide power to the monitor cable must pull this line to Vddq through a pull-up resistor. Table 3-5 is included in this specification to point out the USB signals that might be need by the graphics add-in card. Table 3-6: Power Management on A.G.P. Name Description PME# Power Management Event is not used by the A.G.P protocol, but is used by the PCI target interface when being power managed by the operating system. Refer to the PCI Bus Power Management Interface Specification for the definition of PME# and how a device is power managed by the operating system. Table 3-6 is included in this interface specification to point out the PCI Power Management signal which is used to control the power used by the device. Since an A.G.P. device is also a PCI target, the device follows the PCI Bus Power Management Interface Specification when supporting power management. Care needs to be taken when supporting power management to ensure correct operation and compliance with the power management specification. Table 3-7: Special Interface Signals Name Description TYPEDET# Type detect indicates whether the interface is 1.5 volt or 3.3 volt. Refer to Section 4.3.4 for a description of this signal