电子科技大学：《模拟集成电路分析与设计 Analysis and Design of Analog Integrated Circuit》课程教学资源（教学大纲，负责人：罗萍）

❑ 1.1 Introduction ❑ 1.2 Overview on Manufacturing Process ❑ 1.3 The MOS(FET) Transistor ❑ 1.3.1 I-V/C-V characteristics (self-learning) ❑ 1.3.2 SPICE Models ❑ 1.4 Process Variations

电子科技大学：《高等数字集成电路设计 Advanced Digital Integrated Circuits Design》课程教学资源（教学大纲，负责人：贺雅娟）

Digital Signal Processing • Signal & System • DSP system • Description for DSP FIR Filter Design & Implement • Digital Filter • Specification Design • Hardware Implementation Some Examples • Digital Down Converter • Central Processing Unit

Verilog for Verification • Testbench anatomy • Behavioral modeling for Testbench • Some examples Timing specification • Delay model • Timing verification • Pipeline technology Design For Test (DFT) Test vs. Verification Build In Self Test (BIST) Scan and Boundary Scan

• Synthesizable • Some experiences • Other syntax rules

FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller

• Topics Covered • Requirements • Others Info

• ASIC Classification • Design Flow and tools • Design Domains & Levels

• History, Present & Future • Manufacturing Process • Some Terms