he Ten commandments of excellent design Dowloadfromhttp://www.fpga.com.cn Peter chambers Engineering Fellow VLSI Technology This report will give you some pointers that will help you design synchronous circuits that work first time. Ten commandments that should always be followed Using Synchronous Circuits Synchronous digital systems are pervasive in today's designs Engineers create clocked circuits for every conceivable application, with frequencies from DC to GHz. Every synchronous system employs certain common characteristics, and is prone to a group of common faults. These faults can cause instability and unreliability, and may not be uncovered in the typical design process. The net result is a poor product that fails to meet the design criteria, and the engineer has to go through the suffering of design modification and revision. This is time- consuming and costly. However, by applying a few simple rules, you can avoid synchronous design faults in your designs and achieve consistent first-pass ccess. In this article you'll learn the sources of the most common problems and their solutions, and how to apply these ideas to your designs c1997, VLSI Technology
© 1997, VLSI Technology 1 The Ten Commandments of Excellent Design Dowload from: http:// www.fpga.com.cn Peter Chambers Engineering Fellow VLSI Technology This report will give you some pointers that will help you design synchronous circuits that work first time. Ten commandments that should always be followed! Using Synchronous Circuits Synchronous digital systems are pervasive in today’s designs. Engineers create clocked circuits for every conceivable application, with frequencies from DC to GHz. Every synchronous system employs certain common characteristics, and is prone to a group of common faults. These faults can cause instability and unreliability, and may not be uncovered in the typical design process. The net result is a poor product that fails to meet the design criteria, and the engineer has to go through the suffering of design modification and revision. This is timeconsuming and costly. However, by applying a few simple rules, you can avoid synchronous design faults in your designs and achieve consistent first-pass success. In this article you’ll learn the sources of the most common problems and their solutions, and how to apply these ideas to your designs
igital Systems 101 We'll begin by describing a typical synchronous circuit. Many variations are pos- ible but a simple example will be adequate to illustrate the sources of error Figure 1 shows the circuit and timing for one clocked element of the example One issue that deserves mention is this: Why use synchronous logic at all? Wouldn't asynchronous logic be faster? The answers to these questions could take a book, but here are some reasons to use synchronous designs Synchronous designs eliminate the problems associated with speed varia- tions through different paths of logic. By sampling signals at well-defined time intervals, fast paths and slow paths can be handled in a simple manner Synchronous designs work well under variations of temperature, voltage and process. This stability is key for high-volume manufacturing Many designs must be portable-that is, they must be easy to migrate to a new and improved technology(say, moving from 6 micron to. 35 micron) The deterministic behavior of synchronous designs makes them much more straightforward to move to a new technology Interfacing between two blocks of logic is simplified by defining standardized synchronous behavior. Asynchronous interfaces demand elaborate hand shaking or token passing to ensure integrity of information; synchronous designs with known timing characteristics can guarantee correct reception of Heck, I Know What a Flip Synchronous circuits are made with a mixture of combinatorial logic and Flop Is! clocked elements, such as fiip flops or registers. The clocked elements share a common clock, and all transition from one state to another on the rising edge of The Ten Commandments of Excellent Design
Digital Systems 101 2 The Ten Commandments of Excellent Design Digital Systems 101 We’ll begin by describing a typical synchronous circuit. Many variations are possible, but a simple example will be adequate to illustrate the sources of error. Figure 1 shows the circuit and timing for one clocked element of the example. One issue that deserves mention is this: Why use synchronous logic at all? Wouldn’t asynchronous logic be faster? The answers to these questions could take a book, but here are some reasons to use synchronous designs: • Synchronous designs eliminate the problems associated with speed variations through different paths of logic. By sampling signals at well-defined time intervals, fast paths and slow paths can be handled in a simple manner. • Synchronous designs work well under variations of temperature, voltage and process. This stability is key for high-volume manufacturing. • Many designs must be portable—that is, they must be easy to migrate to a new and improved technology (say, moving from .6 micron to .35 micron). The deterministic behavior of synchronous designs makes them much more straightforward to move to a new technology. • Interfacing between two blocks of logic is simplified by defining standardized synchronous behavior. Asynchronous interfaces demand elaborate handshaking or token passing to ensure integrity of information; synchronous designs with known timing characteristics can guarantee correct reception of data. Heck, I Know What a FlipFlop Is! Synchronous circuits are made with a mixture of combinatorial logic and clocked elements, such as flip flops or registers. The clocked elements share a common clock, and all transition from one state to another on the rising edge of
Digital Systems 101 the clock. When the rising edge occurs, the registers propagate the logic levels at their d inputs to their Q outputs Logic T D FIGURE1. Simple Example of a Synchronous Circuit In Figure 1, two important timing parameters are defined Setup Time-Tsu Setup time is the time that the D input to a register must be valid before the clock transitions Hold Time-Th Hold time is the period that the d input to a register must be maintained valid after the clock has transitioned If the setup or hold time parameters are violated terrible things happen. We'll discuss this later in the section on synchronization The Ten Commandments of Excellent Design
Digital Systems 101 The Ten Commandments of Excellent Design 3 the clock. When the rising edge occurs, the registers propagate the logic levels at their D inputs to their Q outputs. FIGURE 1. Simple Example of a Synchronous Circuit In Figure 1, two important timing parameters are defined: • Setup Time—Tsu Setup time is the time that the D input to a register must be valid before the clock transitions. • Hold Time—Th Hold time is the period that the D input to a register must be maintained valid after the clock has transitioned. If the setup or hold time parameters are violated terrible things happen. We’ll discuss this later in the section on synchronization. D Clock Combinatorial Q Logic Inputs Output Clock D Q Th Tsu
Clock Distribution(Yawn) Clock Distribution(Yawn The distribution of clocks throughout a design has received considerable atten- tion with the increase in logic speed Common-or-garden personal computers have bus speeds of 66 MHz, and processor clocks run at 300 MHz or greater. In this article we're concerned more with the possible pitfalls in the synchronous logic itself, not with the production of decent clocks. However, for completeness here are the important parameters necessary for a good clock distribution sys tem design Skew Minimization Clock skew is the variation in time of the clock's active transition being detected by different devices within a system. Skew must be kept to a mini- mum to ensure that setup and hold times are not violated at any one device Methods for managing skew include equal-length traces, zero-delay PLL based buffers, and additional logic for extending hold times The clock's waveform must be as clean and deterministic as possible. Tech- niques used to guarantee consistent clock behavior include transmission line termination, ground-bounce minimization, and the use of identical clock driv The Ten Commandments of Excellent Design
Clock Distribution (Yawn) 4 The Ten Commandments of Excellent Design Clock Distribution (Yawn) The distribution of clocks throughout a design has received considerable attention with the increase in logic speed. Common-or-garden personal computers have bus speeds of 66 MHz, and processor clocks run at 300 MHz or greater. In this article we’re concerned more with the possible pitfalls in the synchronous logic itself, not with the production of decent clocks. However, for completeness, here are the important parameters necessary for a good clock distribution system design: • Skew Minimization Clock skew is the variation in time of the clock’s active transition being detected by different devices within a system. Skew must be kept to a minimum to ensure that setup and hold times are not violated at any one device. Methods for managing skew include equal-length traces, zero-delay PLLbased buffers, and additional logic for extending hold times. • Clock Fidelity The clock’s waveform must be as clean and deterministic as possible. Techniques used to guarantee consistent clock behavior include transmission line termination, ground-bounce minimization, and the use of identical clock drivers
Good State Machine Design One of the designer,s most powerful constructs for synchronous design is the state machine Combining combinatorial logic and a number of registers, the state machine is capable of making decisions based on its inputs and its current state. The behavior of the state machine is entirely synchronous, with all deci- sions taken at the time of the clock transition there are two conventional forms of state machine: Mealy and moore. The characteristics of these machines are shown in Figure 2. Inputs Combinatorial State Combinatorial Clock Moore machine Combinatoria State Combinatorial Outputs Register ogIc Clock Mealy Machine FIGURE 2. Characteristics of Mealy and Moore Machines Moore machines Moore machines are the simpler of the two standard types. The output is a function only of the current state of the machine Mealy Machines The outputs of Mealy machines are a function of the current state of the machine plus the inputs. This additional path provides more flexibility, but ate the understanding of the ma The Ten Commandments of Excellent Design
Good State Machine Design The Ten Commandments of Excellent Design 5 Good State Machine Design One of the designer’s most powerful constructs for synchronous design is the state machine. Combining combinatorial logic and a number of registers, the state machine is capable of making decisions based on its inputs and its current state. The behavior of the state machine is entirely synchronous, with all decisions taken at the time of the clock transition. There are two conventional forms of state machine: Mealy and Moore. The characteristics of these machines are shown in Figure 2. FIGURE 2. Characteristics of Mealy and Moore Machines • Moore Machines Moore machines are the simpler of the two standard types. The output is a function only of the current state of the machine. • Mealy Machines The outputs of Mealy machines are a function of the current state of the machine plus the inputs. This additional path provides more flexibility, but may complicate the understanding of the machine. Clock State Combinatorial Logic Inputs Combinatorial Outputs Logic Register Mealy Machine Clock State Combinatorial Logic Inputs Combinatorial Outputs Logic Register Moore Machine