Good State Machine Design Books on high-level design languages(HDLs)expound at great length on the construction of state machines. The results are frequently disappointing. If you define your state machine in an HDL and run your design through a synthesizer, you may find spaghetti logic that no self-respecting designer would ever put together. What's Wrong with Mealy/ Figure 2 shows that the outputs of both the mealy and Moore forms of state Moore? machine are combinatorial decodes of the current state and, in the Mealy form the inputs. While this is fine in principle, there are pitfalls here waiting to trap the The outputs of the state machine may include the following types of function Latch enables(low-or high-going pulses to open or close latches) Tristate enables(signals to turn on and off drivers onto on-chip or off-chip Register enables(enables to synchronously clocked registers) Other general control signals, such as counter enables, flags, and so on Most of these signals have one characteristic in common-glitches are abso lutely unacceptable at any time. As the state registers and inputs of the Mealy or Moore state machines transition and settle, the combinatorial gates are quite capable of generating glitches as a consequence of the varying gate propaga- tion delays. These transitory glitches may well contain enough energy to open latches, clock registers, and other highly undesirable effects Wouldn't Gray Code Fix the We all learn at an early age that gray code counters are wonderful since only one bit changes at a time When fed to an asynchronous decoder, theory sug- gests that the outputs should settle to their new state without noise. Your author is suspicious of this when the implementation is created by synthesized logic unclocked feed-forward paths might well negate the advantage of gray code There is, however, a greater challenge to the use of gray code. The sequence of transitions taken by a state machine as it does its stuff is likely to be quite elab- rate: many state machines are very complex with many branches between the possible states. Since gray code-driven decodes are only glitch free when a sin gle bit changes at each clock edge, the designer must assure that all possible state transitions result in only a single bit change of the state variable. This is practical in only the simplest of state machines A Much Better State Machine Figure 3 shows a much better design for a state machine. By adding an output register(with cleanly clocked D-type flip-flops) that is reloaded at each clock edge, the outputs of the state machine are guaranteed to be always glitch-free The Ten Commandments of Excellent Design
Good State Machine Design 6 The Ten Commandments of Excellent Design Books on high-level design languages (HDLs) expound at great length on the construction of state machines. The results are frequently disappointing. If you define your state machine in an HDL and run your design through a synthesizer, you may find spaghetti logic that no self-respecting designer would ever put together. What’s Wrong with Mealy/ Moore? Figure 2 shows that the outputs of both the Mealy and Moore forms of state machine are combinatorial decodes of the current state and, in the Mealy form, the inputs. While this is fine in principle, there are pitfalls here waiting to trap the unwary. The outputs of the state machine may include the following types of function: • Latch enables (low- or high-going pulses to open or close latches) • Tristate enables (signals to turn on and off drivers onto on-chip or off-chip buses) • Register enables (enables to synchronously clocked registers) • Other general control signals, such as counter enables, flags, and so on. Most of these signals have one characteristic in common—glitches are absolutely unacceptable at any time. As the state registers and inputs of the Mealy or Moore state machines transition and settle, the combinatorial gates are quite capable of generating glitches as a consequence of the varying gate propagation delays. These transitory glitches may well contain enough energy to open latches, clock registers, and other highly undesirable effects. Wouldn’t Gray Code Fix the Problem? We all learn at an early age that gray code counters are wonderful since only one bit changes at a time. When fed to an asynchronous decoder, theory suggests that the outputs should settle to their new state without noise. Your author is suspicious of this when the implementation is created by synthesized logic; unclocked feed-forward paths might well negate the advantage of gray code. There is, however, a greater challenge to the use of gray code. The sequence of transitions taken by a state machine as it does its stuff is likely to be quite elaborate; many state machines are very complex with many branches between the possible states. Since gray code-driven decodes are only glitch free when a single bit changes at each clock edge, the designer must assure that all possible state transitions result in only a single bit change of the state variable. This is practical in only the simplest of state machines. A Much Better State Machine Figure 3 shows a much better design for a state machine. By adding an output register (with cleanly clocked D-type flip-flops) that is reloaded at each clock edge, the outputs of the state machine are guaranteed to be always glitch-free
Feeding Inputs and Resets to Your State Machine is suggested that all state machines be implemented in this form, since the quality of the outputs is independent of the number of states or outputs State uts Combinatorial Register Outputs Clock FIGURE 3. A Much Better State Machine Feeding Inputs and resets to Your State Machine Reset signals are traditionally asynchronous and are routed directly to the clear inputs of state machine register elements. When the reset is asserted all regis- ters(state and output bits)are cleared immediately. All well and good, but what happens when the reset is deasserted Consider a state machine that will tran- sition from the reset state to some other state directly after the reset is deas- serted. If the reset deasserts close to a clock edge, some of the state bits will assume their new states, while others might not. The state machine ends up in an undefined error state, and, yet again, you have egg on your face The solution? Synchronize that darned reset! That way, the reset will be removed well before the clock edge, and all register elements will correctly tran- sition to their new states Synchronize A∥ State In fact, every input to your state machine must be synchronous At the very Machine Inputs least, you must be absolutely certain that no input will violate the setup and hold times of the state machine's state and output registers The Ten Commandments of Excellent Design
Feeding Inputs and Resets to Your State Machine The Ten Commandments of Excellent Design 7 It is suggested that all state machines be implemented in this form, since the quality of the outputs is independent of the number of states or outputs. FIGURE 3. A Much Better State Machine Feeding Inputs and Resets to Your State Machine Reset signals are traditionally asynchronous and are routed directly to the clear inputs of state machine register elements. When the reset is asserted, all registers (state and output bits) are cleared immediately. All well and good, but what happens when the reset is deasserted? Consider a state machine that will transition from the reset state to some other state directly after the reset is deasserted. If the reset deasserts close to a clock edge, some of the state bits will assume their new states, while others might not. The state machine ends up in an undefined error state, and, yet again, you have egg on your face. The solution? Synchronize that darned reset! That way, the reset will be removed well before the clock edge, and all register elements will correctly transition to their new states. Synchronize All State Machine Inputs In fact, every input to your state machine must be synchronous. At the very least, you must be absolutely certain that no input will violate the setup and hold times of the state machine’s state and output registers. Clock State Combinatorial Logic Inputs Outputs Register Output Register