A 975 to 1960 MHz,Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners Lei Lu1,2,Zhichao Gong1.2,Youchun Liao2, Hao Min1,Zhangwen Tang 1 Fudan University,Shanghai,China 2 Ratio Microelectronics,Shanghai,China 件
A 975 to 1960 MHz, Fast-Locking FractionalN Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners Lei Lu1,2, Zhichao Gong1,2, Youchun Liao 2 , Hao Min 1, Zhangwen Tang 1 1 Fudan University, Shanghai, China 2 Ratio Microelectronics, Shanghai, China
Outline ·Motivation Synthesizer Architecture ·Proposed Techniques >Adaptive Bandwidth Control Division-Ratio-Based AFC Technique >4/4.5 Prescaler ·Measurement Results ·Conclusions 2009 IEEE International Solid-State Circuits Conference 2009 IEEE
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 2 Outline • Motivation • Synthesizer Architecture • Proposed Techniques ¾Adaptive Bandwidth Control ¾Division-Ratio-Based AFC Technique ¾4/4.5 Prescaler • Measurement Results • Conclusions
Motivation Digital TV tuners need a wideband frequency synthesizer such as DVB-T Loop bandwidth changes greatly during a wide frequency range Wideband VCO needs AFC to select the sub- band automatically Low phase noise and low phase error are required in the receiver 2009 IEEE International Solid-State Circuits Conference 2009 IEEE 3
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 3 Motivation • Digital TV tuners need a wideband frequency synthesizer such as DVB-T • Loop bandwidth changes greatly during a wide frequency range • Wideband VCO needs AFC to select the subband automatically • Low phase noise and low phase error are required in the receiver
Pros Cons ·Advantages Loop bandwidth is adaptively controlled Residual fractional error is reduced and VCO clock is counted directly Lower phase noise due to the 4/4.5 prescaler Measured low phase noise,low phase error and fast locking time ·Disadvantages >The 4/4.5 prescaler leads to a little bit higher power The fractional spur is high when fractional modulus is close to 0 or 1 2009 IEEE International Solid-State Circuits Conference 2009 IEEE
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 4 Pros & Cons • Advantages ¾ Loop bandwidth is adaptively controlled ¾ Residual fractional error is reduced and VCO clock is counted directly ¾ Lower phase noise due to the 4/4.5 prescaler ¾ Measured low phase noise, low phase error and fast locking time • Disadvantages ¾ The 4/4.5 prescaler leads to a little bit higher power ¾ The fractional spur is high when fractional modulus is close to 0 or 1
Synthesizer Block Diagram 8 8 AFC 4 MSBs fref 25MHZ 2 千o PFD 0.975~ 1.96GHz R 尘 S2 LPF VCO Differential CP Double-edge P/S Prescaler Retiming Counter 4/4.5 F2202929 3rd-order 3 9 DSM 9 Dithering N[7:0]+.F[23] 2009 IEEE International Solid-State Circuits Conference 2009 IEEE 5
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 5 Synthesizer Block Diagram LPF Prescaler 4/4.5 P/S Counter Double-edge Retiming PFD 3rd-order DSM Dithering AFC 8 Vref fref s1 25MHz s1 R1 R1 C1/2 C 2 C 2 R 3 R 3 C 3 C 3 Vref s1 s1 s 2 s 2 VCO fout 0.975~ 1.96GHz 23 3 23 .F[22:0] N[7:0]+.F[23] 9 9 Differential CP 4 MSBs 8