928 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 An 18-mW 1.175-2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners Lei Lu,Student Member,IEEE,Jinghong Chen,Senior Member,IEEE, Lu Yuan,Hao Min,and Zhangwen Tang,Member;IEEE Abstract-A fully integrated 1.175-2-GHz differentially tuned-87 dBc/Hz at a 10-kHz offset [2].In addition,because of the frequency synthesizer aimed for digital video broadcasting-ter- very wide frequency range,the synthesizer loop bandwidth, restrial tuners is implemented in a 0.18-um CMOS process. which affects the phase-noise optimization and loop stability. To maintain phase-noise optimization and loop stability over the entire output frequency range,techniques of constant loop may vary quite significantly due to two reasons.Firstly,to bandwidth are proposed.The voltage-controlled oscillator gain cover such a wideband frequency range and achieve a rela- Kvco and band step fr are both maintained by simultaneously tively low voltage-controlled oscillator (VCO)gain (Kvco),a adjusting the sizes of switched capacitors and varactors.Charge switched capacitor array is usually employed in the LC VCO. pump current Icp is programmed to compensate the variation of the division ratio N.The measured results show an in-band phase However,even with a switched capacitor bank,the VCO gain noise of-97.6 dBc/Hz at a 10-kHz offset and an integrated phase variation is still huge.The phase noise is degraded as the VCO error of 0.630 from 100 Hz to 10 MHz.The measured variations of gain increases [3].Secondly,a large range of division ratio Kvco and fres are less than 12.5%and 4.5%,respectively.The N is required to obtain the wide tuning range of nearly one variations of the measured phase noise at 10-kHz and 1-MHz fre- octave.The N variation also changes the loop bandwidth,thus quency offsets are less than 1 dB.The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%.The chip impacting the phase noise and loop stability. draws 10-mA current from a 1.8-V supply while occupying a To achieve a constant loop bandwidth,several methods have 2.2-mm2 die area. been previously proposed [4],[5].In [4],natural frequency wn Index Terms-Frequency synthesizer,loop bandwidth,loop gain, is used as a definition of the loop bandwidth.To handle the large phase noise,voltage-controlled oscillator(VCO)gain,wideband. division ratio range,a sampled loop filter (LPF)network is con- structed and an inverse-linear charge pump(CP)is used to keep the natural frequency over reference frequency (wn/wref)and I.INTRODUCTION the damping factor constant.Though the natural frequency HE DIGITAL video broadcasting-terrestrial (DVB-T)and damping factor are widely used in the analysis of synthe- standard has ushered in a new era in TV entertainment. sizer loop dynamic,strictly speaking,they are applicable only Often the DVB-T tuners employ a double-conversion zero-IF to second-order loops.The inverse-linear CP also adds design (DZIF)architecture,which demands the use of a wideband complexity.Reference [5]uses open-loop crossover frequency frequency synthesizer as the first local oscillator (LO)(LO)We as the loop bandwidth and adjusts only the CP current(ICp) to cover the 48-862-MHz-wide frequency range and a frac- to compensate the Kvco and N variations.Although the open- tional-N frequency synthesizer as the second LO (LO2)to loop crossover frequency is often used to define a loop band- support several channel bandwidths(6/7/8 MHz)[1],[2]. width,it cannot accurately capture the low-pass corner charac- There are many challenges in designing a wideband fre-teristics of the closed-loop transfer function.In addition,though quency synthesizer LO1.It must achieve a wide frequency adjusting Icp alone can achieve a constant loop bandwidth,a tuning range,while providing low phase noise and low in-multiband VCO with constant and smaller gains is still desired tegrated phase error.The wideband synthesizer LO needs in order to improve the phase-noise performance. to meet a stringent phase-noise requirement over the entire In this paper,the concept of loop gain is used as the loop frequency range,which should be larger than the input range bandwidth to accurately model the low-pass characteristics of of 814 MHz.An adequate target for the overall phase noise is the closed-loop transfer function.Techniques achieving a con- stant and smaller VCO gain Kvco while obtaining a constant Manuscript received July 31,2008:revised December 19,2008.First loop bandwidth are proposed [6].Both a constant Kvco and published March 10,2009:current version published April 08.2009.This an equal band step fres are obtained in a multiband VCO.Au- work was supported in part by the National 863 Program of China under Grant 2007AA01Z282 and the National Science Funding of China under Grant tomatic frequency control (AFC)is used to ensure the opera- 60876019. tion of VCO in the linear region of the tuning range.The VCO L.Lu,L.Yuan,H.Min,and Z.Tang are with the Application Specific In- tegrated Circuit (ASIC)and System State Key Laboratory.Fudan University, with equal band steps greatly helps to simplify the AFC loop de- Shanghai 201203,China (e-mail:zwtang@fudan.edu.cn). sign.Programmable CP current is also adopted to compensate J.Chen is with Analog Devices Inc.,Somerset,NJ 08873 USA (e-mail: the variation of the division ratio N. jinghong@ieee.org). Color versions of one or more of the figures in this paper are available online The remainder of this paper is organized as follows.In at http://ieeexplore.ieee.org. Section II,design issues of the frequency synthesizer are con- Digital Object Identifier 10.1109/TMTT.2009.2014449 sidered and the loop gain is derived.The KVCo variation in a 0018-9480/s25.00©2009EEE
928 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners Lei Lu, Student Member, IEEE, Jinghong Chen, Senior Member, IEEE, Lu Yuan, Hao Min, and Zhangwen Tang, Member, IEEE Abstract—A fully integrated 1.175–2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-terrestrial tuners is implemented in a 0.18- m CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain and band step are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current is programmed to compensate the variation of the division ratio . The measured results show an in-band phase noise of 97.6 dBc Hz at a 10-kHz offset and an integrated phase error of 0.63 from 100 Hz to 10 MHz. The measured variations of and are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz frequency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm die area. Index Terms—Frequency synthesizer, loop bandwidth, loop gain, phase noise, voltage-controlled oscillator (VCO) gain, wideband. I. INTRODUCTION T HE DIGITAL video broadcasting-terrestrial (DVB-T) standard has ushered in a new era in TV entertainment. Often the DVB-T tuners employ a double-conversion zero-IF (DZIF) architecture, which demands the use of a wideband frequency synthesizer as the first local oscillator (LO) to cover the 48–862-MHz-wide frequency range and a fractional- frequency synthesizer as the second LO to support several channel bandwidths (6/7/8 MHz) [1], [2]. There are many challenges in designing a wideband frequency synthesizer . It must achieve a wide frequency tuning range, while providing low phase noise and low integrated phase error. The wideband synthesizer needs to meet a stringent phase-noise requirement over the entire frequency range, which should be larger than the input range of 814 MHz. An adequate target for the overall phase noise is Manuscript received July 31, 2008; revised December 19, 2008. First published March 10, 2009; current version published April 08, 2009. This work was supported in part by the National 863 Program of China under Grant 2007AA01Z282 and the National Science Funding of China under Grant 60876019. L. Lu, L. Yuan, H. Min, and Z. Tang are with the Application Specific Integrated Circuit (ASIC) and System State Key Laboratory, Fudan University, Shanghai 201203, China (e-mail: zwtang@fudan.edu.cn). J. Chen is with Analog Devices Inc., Somerset, NJ 08873 USA (e-mail: jinghong@ieee.org). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2009.2014449 87 dBc Hz at a 10-kHz offset [2]. In addition, because of the very wide frequency range, the synthesizer loop bandwidth, which affects the phase-noise optimization and loop stability, may vary quite significantly due to two reasons. Firstly, to cover such a wideband frequency range and achieve a relatively low voltage-controlled oscillator (VCO) gain , a switched capacitor array is usually employed in the VCO. However, even with a switched capacitor bank, the VCO gain variation is still huge. The phase noise is degraded as the VCO gain increases [3]. Secondly, a large range of division ratio is required to obtain the wide tuning range of nearly one octave. The variation also changes the loop bandwidth, thus impacting the phase noise and loop stability. To achieve a constant loop bandwidth, several methods have been previously proposed [4], [5]. In [4], natural frequency is used as a definition of the loop bandwidth. To handle the large division ratio range, a sampled loop filter (LPF) network is constructed and an inverse-linear charge pump (CP) is used to keep the natural frequency over reference frequency and the damping factor constant. Though the natural frequency and damping factor are widely used in the analysis of synthesizer loop dynamic, strictly speaking, they are applicable only to second-order loops. The inverse-linear CP also adds design complexity. Reference [5] uses open-loop crossover frequency as the loop bandwidth and adjusts only the CP current to compensate the and variations. Although the openloop crossover frequency is often used to define a loop bandwidth, it cannot accurately capture the low-pass corner characteristics of the closed-loop transfer function. In addition, though adjusting alone can achieve a constant loop bandwidth, a multiband VCO with constant and smaller gains is still desired in order to improve the phase-noise performance. In this paper, the concept of loop gain is used as the loop bandwidth to accurately model the low-pass characteristics of the closed-loop transfer function. Techniques achieving a constant and smaller VCO gain while obtaining a constant loop bandwidth are proposed [6]. Both a constant and an equal band step are obtained in a multiband VCO. Automatic frequency control (AFC) is used to ensure the operation of VCO in the linear region of the tuning range. The VCO with equal band steps greatly helps to simplify the AFC loop design. Programmable CP current is also adopted to compensate the variation of the division ratio . The remainder of this paper is organized as follows. In Section II, design issues of the frequency synthesizer are considered and the loop gain is derived. The variation in a 0018-9480/$25.00 © 2009 IEEE
LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 929 LPF fout=N-fre Binary weighted CP apa r array ÷N Fig.1.Block diagram of an integer-N frequency synthesizer with a typical passive LPF. (a) wideband PLL design is also investigated.Section III proposes techniques to achieve a constant Kyco and loop bandwidth. 2.2×10 Kvco_max=320MHz/V F-V curve The circuit implementation is described in Section IV.The ex- perimental results are given in Section V,and finally,Section VI concludes this study. 1,8 II.DESIGN CONSIDERATIONS 16 Kvco_max=8 Kyco min A.Loop Gain The phase-locked loop(PLL)loop bandwidth is an impor- fres min= tant design parameter for minimizing phase-noise variation and Kkv_in=40MHz/ 26MHz guaranteeing loop stability.As mentioned earlier,it is often de- 0.4 0.6 0.8 1.2 14 sired to have a constant loop bandwidth over the entire fre- Tuning Voltage (V) quency range. (b) The block diagram of an integer-N third-order type-II PLL is shown in Fig.1,which includes a phase-frequency detector Fig.2.Conventional topology.(a)Switching capacitor array and one varactor unit.(b)F-Vcurve with large variations of VCO tuning gain and band step. (PFD),a CP,a second-order passive LPF,an LC VCO,and a di- vider.Often the natural frequency wn or the open-loop crossover frequency wc is used as the loop bandwidth;however,the former For a typical third-order PLL,the transfer function of the LPF is not applicable in third or higher order loops and strongly de- is obtained as pends on the damping factor C,while the latter cannot capture 1 1 the low-pass corner characteristics of the closed-loop transfer (3) function.In this paper,the loop gain K is used to model the FLPF()=RIC (1+RC]s)RCCas+C+C low-pass corner of the closed-loop transfer function [7].[8].where K1 is equal to RiC and Fhf(0)is equal to 1/(C+ The open-loop transfer function of a PLL with a general LPF C2).Therefore,the loop gain K of the third-order PLL can be FLPF(s)is expressed as rewritten as G(s)= ICPKVCO FLPF(s)= K=ICPKvcoR b 2TN b+1 (4) 2INs IcpKvcO F+i(s)Fit(s) 2nNs ICPKvco where b is the ratio of Cl over C2.It can be observed that to 2nNs K1+ K2+…Ff() achieve a constant loop gain without changing the pole and zero positions is to maintain a constant VCO gain KVco and to make ICpKvcoK1Fhf(0) K2 Fir(s) 1+ (1) the CP current ICp match N. 2nNs K1s 十· Fir(O B.VCO Gain where ICp is the sink or source current of the CP.The Fpi(s) Frequency synthesizers for RF receivers usually employ an represents the proportional and integral components of the LPF, LC-based VCO due to its superior phase-noise performance. and Fif(s)represents the high-frequency components of the For the DVB-T frequency synthesizer,the targeted 814-MHz LPF.Note that Ff(0)is a finite and nonzero number.Thus. frequency range requires a VCO gain of more than 500 MHz/V the loop gain K is given by [7] assuming a 1.6-V tuning range for the CP output voltage.Such a high Kvco may significantly degrade the phase-noise per- K=IcpKvcoKi Ft(0) formance.To cover a wideband frequency range with a smaller rad/s (2) 2nN KvCo,a switched capacitor array is usually adopted,as shown in Fig.2(a).A fixed varactor Cu is tuned by the analog control Note that K has a unit of radians/second. voltage Vetri to achieve a continuous VCO frequency tuning
LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 929 Fig. 1. Block diagram of an integer- frequency synthesizer with a typical passive LPF. wideband PLL design is also investigated. Section III proposes techniques to achieve a constant and loop bandwidth. The circuit implementation is described in Section IV. The experimental results are given in Section V, and finally, Section VI concludes this study. II. DESIGN CONSIDERATIONS A. Loop Gain The phase-locked loop (PLL) loop bandwidth is an important design parameter for minimizing phase-noise variation and guaranteeing loop stability. As mentioned earlier, it is often desired to have a constant loop bandwidth over the entire frequency range. The block diagram of an integer- third-order type-II PLL is shown in Fig. 1, which includes a phase-frequency detector (PFD), a CP, a second-order passive LPF, an VCO, and a divider. Often the natural frequency or the open-loop crossover frequency is used as the loop bandwidth; however, the former is not applicable in third or higher order loops and strongly depends on the damping factor , while the latter cannot capture the low-pass corner characteristics of the closed-loop transfer function. In this paper, the loop gain is used to model the low-pass corner of the closed-loop transfer function [7], [8]. The open-loop transfer function of a PLL with a general LPF is expressed as (1) where is the sink or source current of the CP. The represents the proportional and integral components of the LPF, and represents the high-frequency components of the LPF. Note that is a finite and nonzero number. Thus, the loop gain is given by [7] rad/s (2) Note that has a unit of radians/second. Fig. 2. Conventional topology. (a) Switching capacitor array and one varactor unit. (b) – curve with large variations of VCO tuning gain and band step. For a typical third-order PLL, the transfer function of the LPF is obtained as (3) where is equal to and is equal to . Therefore, the loop gain of the third-order PLL can be rewritten as (4) where is the ratio of over . It can be observed that to achieve a constant loop gain without changing the pole and zero positions is to maintain a constant VCO gain and to make the CP current match . B. VCO Gain Frequency synthesizers for RF receivers usually employ an -based VCO due to its superior phase-noise performance. For the DVB-T frequency synthesizer, the targeted 814-MHz frequency range requires a VCO gain of more than 500 MHz/V assuming a 1.6-V tuning range for the CP output voltage. Such a high may significantly degrade the phase-noise performance. To cover a wideband frequency range with a smaller , a switched capacitor array is usually adopted, as shown in Fig. 2(a). A fixed varactor is tuned by the analog control voltage to achieve a continuous VCO frequency tuning,
930 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 while a binary weighted capacitor array is controlled digitally Size changeable to discretely change the frequency band. capacitor array Although the switched capacitor array can extend the VCO Cr tuning range while maintaining a smaller KvCo,it has two dis- en a1Cf advantages.Firstly,equal capacitor is switched in or out of the capacitor bank whenever a lower or higher adjacent tuning band a1sC is required.Due to the nonlinear characteristic of frequency versus capacitance,the Kvco will vary by a factor of 8 when the output frequency doubles by reducing the tank capacitance to a quarter [9].Simulated tuning curves of a wideband VCO from 1 to 2 GHz are shown in Fig.2(b),where a tank induc- tance of 4 nH is used.The highest and lowest Kvco is 320 and 40 MHz/V,respectively.Such a large VCO gain variation sig- nificantly changes the loop bandwidth.As a result,the phase noise is deteriorated and the PLL loop becomes unstable.Sec- ondly,the highest and lowest band step fres is 174 and 26 MHz, Size changeable varactor array respectively.Such a large band-step difference with a ratio of (a) 6.7 greatly increases the complexity of the AFC loop design. 2.2*109 -F-V curve fres=67MHz Kvco=100MHz/V III.DESIGN TECHNIQUES A.Wideband VCO With Constant VCO Gain and Band Step 1.8 The Kvco variation is a severe problem in designing wide- band VCOs.Several techniques have been previously reported to reduce Kvco fluctuation [10].[11].In [10],an additional anba serial LC-tank with a variable inductor configuration is used to offset the VCO gain variation;however,such a method requires extra inductors and consumes more die area.A switched var- actor array in combination with a multibias scheme is used to compensate the Kvco variation in [11].However,this method requires extra complicated biasing networks.In addition,both 0.4 0.6 0.8 1 1.2 1.4 Tuning Voltage (V) techniques cannot solve the variation problem of the band step fres.To minimize variations of both the VCO gain Kyco and (b) the band step fres,a proposed architecture is shown in Fig.3(a). Fig.3.Proposed LC-tank topology.(a)DCCA with a DCVA.(b)F-V curve The idea behind the proposed architecture is to make both with constant VCO tuning gain and band step. the sizes of switched capacitors and the varactors changeable. Instead of using a fixed analog varactor and a binary-weighted across the tank at the center frequency of the nth sub-band can capacitor array,a number of capacitor and varactor units with be expressed as follows: different sizes are adopted.At lower frequency bands,not only more switched capacitor units are connected into the LC-tank, Cp+Cf+(3+…+35)Cw,min+C,0.9, but also more varactor units are connected to the analog control m=1 voltage;the remaining varactor units are connected to a fixed Cp+(1+1+…+anm-1)Cf+(3n+…+35) voltage VB to have a minimum fixed capacitance and the re- Cu,mim+(1++…+3n-1)C,(0.9y maining switched capacitor units are disconnected.On the other Ctot,n n=2,3,,15 hand,at higher frequency bands,less switched capacitor units, Cp+(1+a1+…+15) as well as less varactor units are switched into the LC-tank. .Cf+(1+31+…+315)Cu,0.9): Doing so allows a small and a constant Kvco,as well as a m=16. constant fres to be achieved over the entire frequency range (5) without adding extra design complexity,die area,or power where Cp is the parasitic capacitance,Cf is the capacitance of consumption. the basic switched capacitor unit.Cv,min is the minimum capac- In the synthesizer,a digitally controlled capacitor array itance of the varactor C,and C,(0)is the capacitance of C (DCCA)divides the whole tuning range into 16 sub-bands to at the center of the control voltage(VDD=1.8 V).Note that keep a relatively low analog tuning gain,while an extra digitally n=1 is the highest frequency band.The oscillation frequency controlled varactor array (DCVA)is inserted to equalize the fvco,n at the center of nth sub-band is expressed as tuning sensitivity.Assuming ai(=1,2,...,15)being the capacitor ratio of DCCA units and Bi(=1,2,...,15)being 1 (6) the varactor ratio of DCVA units,the total capacitance Ctot,n fco,n=2m√Ctot,n n=1,2,.…,16
930 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 while a binary weighted capacitor array is controlled digitally to discretely change the frequency band. Although the switched capacitor array can extend the VCO tuning range while maintaining a smaller , it has two disadvantages. Firstly, equal capacitor is switched in or out of the capacitor bank whenever a lower or higher adjacent tuning band is required. Due to the nonlinear characteristic of frequency versus capacitance, the will vary by a factor of 8 when the output frequency doubles by reducing the tank capacitance to a quarter [9]. Simulated tuning curves of a wideband VCO from 1 to 2 GHz are shown in Fig. 2(b), where a tank inductance of 4 nH is used. The highest and lowest is 320 and 40 MHz/V, respectively. Such a large VCO gain variation significantly changes the loop bandwidth. As a result, the phase noise is deteriorated and the PLL loop becomes unstable. Secondly, the highest and lowest band step is 174 and 26 MHz, respectively. Such a large band-step difference with a ratio of 6.7 greatly increases the complexity of the AFC loop design. III. DESIGN TECHNIQUES A. Wideband VCO With Constant VCO Gain and Band Step The variation is a severe problem in designing wideband VCOs. Several techniques have been previously reported to reduce fluctuation [10], [11]. In [10], an additional serial -tank with a variable inductor configuration is used to offset the VCO gain variation; however, such a method requires extra inductors and consumes more die area. A switched varactor array in combination with a multibias scheme is used to compensate the variation in [11]. However, this method requires extra complicated biasing networks. In addition, both techniques cannot solve the variation problem of the band step . To minimize variations of both the VCO gain and the band step , a proposed architecture is shown in Fig. 3(a). The idea behind the proposed architecture is to make both the sizes of switched capacitors and the varactors changeable. Instead of using a fixed analog varactor and a binary-weighted capacitor array, a number of capacitor and varactor units with different sizes are adopted. At lower frequency bands, not only more switched capacitor units are connected into the -tank, but also more varactor units are connected to the analog control voltage; the remaining varactor units are connected to a fixed voltage to have a minimum fixed capacitance and the remaining switched capacitor units are disconnected. On the other hand, at higher frequency bands, less switched capacitor units, as well as less varactor units are switched into the -tank. Doing so allows a small and a constant , as well as a constant to be achieved over the entire frequency range without adding extra design complexity, die area, or power consumption. In the synthesizer, a digitally controlled capacitor array (DCCA) divides the whole tuning range into 16 sub-bands to keep a relatively low analog tuning gain, while an extra digitally controlled varactor array (DCVA) is inserted to equalize the tuning sensitivity. Assuming being the capacitor ratio of DCCA units and being the varactor ratio of DCVA units, the total capacitance Fig. 3. Proposed -tank topology. (a) DCCA with a DCVA. (b) – curve with constant VCO tuning gain and band step. across the tank at the center frequency of the th sub-band can be expressed as follows: (5) where is the parasitic capacitance, is the capacitance of the basic switched capacitor unit, is the minimum capacitance of the varactor , and is the capacitance of at the center of the control voltage V . Note that is the highest frequency band. The oscillation frequency at the center of th sub-band is expressed as (6)
LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 931 where L is half the inductance value of the differential tank in- TABLE I ductor.Furthermore,the VCO gain Kvco.n at the center of the VALUES OF COEFFICIENTS L:AND C nth sub-band,which is derived from the partial derivative of Qi Q i control voltage,can be calculated as 西 1.47 0.11 2.56 0.23 11 5.03 0.56 Kyco,n 2 1.63 0.12 2.90 0.27 12 5.88 0.69 vco.n 1.82 0.14 3.29 0.32 13 6.93 0.87 2.03 0.38 8.24 aVerl 0.16 3.77 1✉ 1.10 2.27 0.19 10 4.34 0.46 15 9.91 1.41 1 aC. m=1 4红√LCgt,n OVetrl V=0.9 1+3+…3m-1. OC 4红V/LCoun OVetrl IVetH=0.9 n=2,3,.,16 (7) where oCu/ovatri(Vetrl =0.9V)is the slope of the C-V curve PFD of the varactor C,at the center of control voltage.Note that OC/Ovtr is negative,hence,Kvco.n is a positive number. For a given constant Kvco and fres,as well as the entire fre- VCO quency range,the procedure to calculate oi and is as follows. Programmable Divider Firstly,the highest frequency band fH,the lowest frequency sda+ ◆N=94-160 band fr,the number of frequency bands n,and the inductance value L are selected,then the center frequency KVco.n at each reset- frequency band can be determined according to the frequency Fig.4.Block-level diagram of a wideband 1.175-2-GHz frequency synthesizer range and the number of bands.Substituting Kvco,n into with differential tuning. (6),Ctot,n can be obtained.Secondly,with the predetermined Kvcon,Ctot,n is substituted into (7)to obtain the coefficients Bi.Thirdly,the inherent capacitance of the cross-coupled MOS senses the VCO output center frequency of each band and com- transistors and the layout parasitic capacitance are estimated pares it with the target value,which is determined by the division to determine the value of Cp.In addition,a varactor unit is ratio N.The AFC loop selects the band whose center frequency simulated to obtain C,min and C,(0.).Finally,by substituting is the closest to the target value [12].[13].As long as the over- Cto,n.Cp,Cf,Cv,min,and Cu,(0.9).as well as the coefficient lapping ratio between any two adjacent bands exceeds 50%,all into(⑤)，the coefficients a;can be obtained. output frequency points can fall near the middle of the tuning Therefore,by choosing oi and Bi properly,the Kvco and curve thus having linear tuning gains.By doing so,the VCO the band step fres can be arbitrary and constant.Nevertheless,it gain variation is further suppressed. should be noted that if MOS transistors are used as the switched C.CP capacitors or the varactors,the minimum channel length of the The frequency synthesizer varies its output frequency by technology may limit the minimum value of the capacitor and varactor sizes and this restricts the Kvco and the band step fres changing the division ratio N.As can be seen from(4),when that can be achieved.An example of the coefficients ai and B is N changes,the loop gain is affected.To compensate the N summarized in Table I when Cp is 1.4 pF.Cf is 73 fF.Cv,(0.9)is variation,the CP current Icp is programmed to match the 40 fF,and C,min is 10 fF.These coefficients should be rounded division ratio N.A number of current mirrors are paralleled with a reference current source and sink to calibrate the total to the nearest values that the technology permits.It should also output charging and discharging current.By adjusting Icp,the be noted that since these coefficients are only ratios,they are insensitive to the process,voltage,and temperature(PVT)vari- term ICr/N can be made unchanged.With a constant IcP/N ations.The simulated tuning curves of the proposed architecture and Kvco,a constant loop gain K can be achieved across the are shown in Fig.3(b).Across the entire frequency range from entire frequency tuning range. 1 to 2 GHz,fres is 67 MHz uniformly and Kyco is 100 MHz/V IV.CIRCUIT IMPLEMENTATION for every switching band. A.System Architecture B.AFC A block-level diagram of the wideband 1.175-2-GHz fre- Due to the nonlinearity of the C-V curve of the varactor,the quency synthesizer is shown in Fig.4.The synthesizer is fully KyCo of each frequency band can only be made equal in the integrated including a PFD,a rail-to-rail differential CP,a dif- middle of the tuning curve.For each tuning curve,the slope ferential passive LPF,a wideband LC VCO,a programmable around the middle is linear and maximal.The AFC algorithm divider,a low drop-out(LDO)regulator,an AFC block,and an
LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 931 where is half the inductance value of the differential tank inductor. Furthermore, the VCO gain at the center of the th sub-band, which is derived from the partial derivative of control voltage, can be calculated as (7) where V is the slope of the – curve of the varactor at the center of control voltage. Note that is negative, hence, is a positive number. For a given constant and , as well as the entire frequency range, the procedure to calculate and is as follows. Firstly, the highest frequency band , the lowest frequency band , the number of frequency bands , and the inductance value are selected, then the center frequency at each frequency band can be determined according to the frequency range and the number of bands. Substituting into (6), can be obtained. Secondly, with the predetermined , is substituted into (7) to obtain the coefficients . Thirdly, the inherent capacitance of the cross-coupled MOS transistors and the layout parasitic capacitance are estimated to determine the value of . In addition, a varactor unit is simulated to obtain and . Finally, by substituting , and , as well as the coefficient into (5), the coefficients can be obtained. Therefore, by choosing and properly, the and the band step can be arbitrary and constant. Nevertheless, it should be noted that if MOS transistors are used as the switched capacitors or the varactors, the minimum channel length of the technology may limit the minimum value of the capacitor and varactor sizes and this restricts the and the band step that can be achieved. An example of the coefficients and is summarized in Table I when is 1.4 pF, is 73 fF, is 40 fF, and is 10 fF. These coefficients should be rounded to the nearest values that the technology permits. It should also be noted that since these coefficients are only ratios, they are insensitive to the process, voltage, and temperature (PVT) variations. The simulated tuning curves of the proposed architecture are shown in Fig. 3(b). Across the entire frequency range from 1 to 2 GHz, is 67 MHz uniformly and is 100 MHz/V for every switching band. B. AFC Due to the nonlinearity of the – curve of the varactor, the of each frequency band can only be made equal in the middle of the tuning curve. For each tuning curve, the slope around the middle is linear and maximal. The AFC algorithm TABLE I VALUES OF COEFFICIENTS AND Fig. 4. Block-level diagram of a wideband 1.175–2-GHz frequency synthesizer with differential tuning. senses the VCO output center frequency of each band and compares it with the target value, which is determined by the division ratio . The AFC loop selects the band whose center frequency is the closest to the target value [12], [13]. As long as the overlapping ratio between any two adjacent bands exceeds 50%, all output frequency points can fall near the middle of the tuning curve thus having linear tuning gains. By doing so, the VCO gain variation is further suppressed. C. CP The frequency synthesizer varies its output frequency by changing the division ratio . As can be seen from (4), when changes, the loop gain is affected. To compensate the variation, the CP current is programmed to match the division ratio . A number of current mirrors are paralleled with a reference current source and sink to calibrate the total output charging and discharging current. By adjusting , the term can be made unchanged. With a constant and , a constant loop gain can be achieved across the entire frequency tuning range. IV. CIRCUIT IMPLEMENTATION A. System Architecture A block-level diagram of the wideband 1.175–2-GHz frequency synthesizer is shown in Fig. 4. The synthesizer is fully integrated including a PFD, a rail-to-rail differential CP, a differential passive LPF, a wideband VCO, a programmable divider, a low drop-out (LDO) regulator, an AFC block, and an
932 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 1.5V,from LDO B15C -0000 an鸠 区en b[3:0]-Encode 015 h 感4丽 Fig.5.Circuit diagram of the proposed wideband LC VCO. 12C controller.In order to suppress common-mode noise from total of 16 sub-bands are achieved.An encoder is used to trans- control lines,power supply,and the substrate,a differentially form binary codes into thermometer codes to control the dig- tuned LC VCO was implemented [14].Accordingly,the CP ital bits.A basic varactor unit of only I-MOS is used at the of the synthesizer was also implemented as a fully differential highest frequency band.The DCCA using I-NMOS transistors structure.When switch S is closed,the differential control volt- performs coarse tuning.When eni(=1,...,15)is high,the ages Vtrlp and Vetrin are connected to a reference voltage Vief, NMOS transistor operates in the strong inversion region and and the AFC loop counts the clock divided by eight from the maximum capacitance is realized.To meet the wideband fre- VCO output and performs the coarse tuning.After AFC oper- quency resonating characteristics,switched capacitor arrays are ation,switch S2 is closed and S is open,and the differential also added at the tail nodes to compensate the tail capacitance control voltages are connected to the CP output to carry out the and allow the tail nodes to oscillate at twice the resonant fre- analog fine tuning.Internal digital registers are configured by an quency over the entire tuning range. T2C controller. The detail realization of DCVA is also depicted.When en is high,Ma and Ms are off,M2-M3 and M6-M7 are on to B.Wideband VCO conduct the control voltage Vetrlp and Vetrin to the drain-source of M and M5,then Mi and M5 are analog controlled and act as The schematic of an LC VCO is illustrated in Fig.5.To varactors.On the other hand,when en is low,the drain-source reduce supply noise coupling,the VCO core is biased by a of M is connected to ground and the drain-source of M is 1.5-V power supply from an on-chip LDO.Two complementary connected to Vpp,thus the capacitances of the varactor Mi and cross-coupled NMOS and PMOS transistors are adopted to form Ms are fixed and set at the minimal value. the negative transconductance.The LC tank uses a differential The quality factor Q of the resonator tank is mainly limited by inductor to achieve a higher O factor compared to single-ended the tank inductor.The differential inductor in the tank is mod- inductors.The tail current source has been removed to improve eled using the Agilent full-wave EM simulator Momentum,and the phase noise in the 1/f3 region.Removing the tail current the inductor Q factor is between 6-10 from 1 to 2 GHz.All the source also maximizes the oscillation amplitude to nearly full capacitors and varactors are made using inversion-mode MOS swing.A tail LC-tank is used to increase the impedance of the transistors,and their factors are optimized between 20-30 tail nodes at the second harmonic,thus eliminating the thermal across the entire tuning range so as to obtain larger values than noise at twice the oscillation frequency.It also enhances the av-that of the inductor. erage loaded Q factor of the resonant LC-tank over one period improving the VCO phase-noise performance [15]. C.Differential CP Inversion-mode MOS(I-MOS)varactors are used to perform A differential CP is used to achieve a better immunity to analog fine tuning [16],[17].To cover the wide frequency range common-mode,power supply,and substrate noises.The con- of more than 814 MHz,four digital control bits are used and a ventional differential CP topology,despite the use of common-
932 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 Fig. 5. Circuit diagram of the proposed wideband VCO. controller. In order to suppress common-mode noise from control lines, power supply, and the substrate, a differentially tuned VCO was implemented [14]. Accordingly, the CP of the synthesizer was also implemented as a fully differential structure. When switch is closed, the differential control voltages and are connected to a reference voltage , and the AFC loop counts the clock divided by eight from the VCO output and performs the coarse tuning. After AFC operation, switch is closed and is open, and the differential control voltages are connected to the CP output to carry out the analog fine tuning. Internal digital registers are configured by an controller. B. Wideband VCO The schematic of an VCO is illustrated in Fig. 5. To reduce supply noise coupling, the VCO core is biased by a 1.5-V power supply from an on-chip LDO. Two complementary cross-coupled NMOS and PMOS transistors are adopted to form the negative transconductance. The tank uses a differential inductor to achieve a higher factor compared to single-ended inductors. The tail current source has been removed to improve the phase noise in the region. Removing the tail current source also maximizes the oscillation amplitude to nearly full swing. A tail -tank is used to increase the impedance of the tail nodes at the second harmonic, thus eliminating the thermal noise at twice the oscillation frequency. It also enhances the average loaded factor of the resonant -tank over one period improving the VCO phase-noise performance [15]. Inversion-mode MOS ( -MOS) varactors are used to perform analog fine tuning [16], [17]. To cover the wide frequency range of more than 814 MHz, four digital control bits are used and a total of 16 sub-bands are achieved. An encoder is used to transform binary codes into thermometer codes to control the digital bits. A basic varactor unit of only -MOS is used at the highest frequency band. The DCCA using -NMOS transistors performs coarse tuning. When is high, the NMOS transistor operates in the strong inversion region and maximum capacitance is realized. To meet the wideband frequency resonating characteristics, switched capacitor arrays are also added at the tail nodes to compensate the tail capacitance and allow the tail nodes to oscillate at twice the resonant frequency over the entire tuning range. The detail realization of DCVA is also depicted. When is high, and are off, – and – are on to conduct the control voltage and to the drain–source of and , then and are analog controlled and act as varactors. On the other hand, when is low, the drain–source of is connected to ground and the drain–source of is connected to , thus the capacitances of the varactor and are fixed and set at the minimal value. The quality factor of the resonator tank is mainly limited by the tank inductor. The differential inductor in the tank is modeled using the Agilent full-wave EM simulator Momentum, and the inductor factor is between 6–10 from 1 to 2 GHz. All the capacitors and varactors are made using inversion-mode MOS transistors, and their factors are optimized between 20–30 across the entire tuning range so as to obtain larger values than that of the inductor. C. Differential CP A differential CP is used to achieve a better immunity to common-mode, power supply, and substrate noises. The conventional differential CP topology, despite the use of common-