ADIS16210 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN1- PIN 15 PIN 15- PIN 1- TOP VIEW BOTTOM VIEW NOTES 1.LEADS ARE EXPOSED COPPER PADS LOCATED ON THE BOTTOM SIDE OF THE FLEXIBLE INTERFACE CABLE. 2.PACKAGE IS NOT SUITABLE FOR SOLDER REFLOW ASSEMBLY PROCESSES. 3.EXAMPLE MATING CONNECTOR:AVX CORPORATION FLAT FLEXIBLE CONNECTOR (FFC) P/:04-6288-015-000-846 Figure 4.Pin Configuration Table 5.Pin Function Descriptions Pin No. Mnemonic Type Description 1,2 VDD Power Supply,3.3 V. 3,4,5,8 GND Ground. 6,9 DNC Do Not Connect.Do not connect to these pins > DIO2 VO Digital Input/Output Line 2. 10 RST Reset,Active Low. 11 DIN SPl,Data Input. 12 DOUT 0 SPl,Data Output.DOUT is an output when CS is low.When CS is high,DOUT is in a three-state,high impedance mode. 13 SCLK SPI,Serial Clock. 14 CS SPI,Chip Select. 15 DIO1 1/O Digital Input/Output Line 1. s is supply,O is output,Iis input,and l/O is input/output. Rev.A|Page 6of 20
ADIS16210 Rev. A | Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 09593-004 TOP VIEW BOTTOM VIEW PIN 15 PIN 15 PIN 1 PIN 1 NOTES 1. LEADS ARE EXPOSED COPPER PADS LOCATED ON THE BOTTOM SIDE OF THE FLEXIBLE INTERFACE CABLE. 2. PACKAGE IS NOT SUITABLE FOR SOLDER REFLOW ASSEMBLY PROCESSES. 3. EXAMPLE MATING CONNECTOR: AVX CORPORATION FLAT FLEXIBLE CONNECTOR (FFC) P/N: 04-6288-015-000-846. Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 2 VDD S Power Supply, 3.3 V. 3, 4, 5, 8 GND S Ground. 6, 9 DNC I Do Not Connect. Do not connect to these pins. 7 DIO2 I/O Digital Input/Output Line 2. 10 RST I Reset, Active Low. 11 DIN I SPI, Data Input. 12 DOUT O SPI, Data Output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode. 13 SCLK I SPI, Serial Clock. 14 CS I SPI, Chip Select. 15 DIO1 I/O Digital Input/Output Line 1. 1 S is supply, O is output, I is input, and I/O is input/output
ADIS16210 BASIC OPERATION The ADIS16210 is an autonomous system that requires no user READING SENSOR DATA initialization.Upon receiving a valid power supply,it initializes A single register read requires two 16-bit SPI cycles.The first itself and starts sampling,processing,and loading data into the cycle requests the contents of a register using the bit assignments output registers.When using the factory default configuration, in Figure9.The register contents then follow on DOUT,during DIO1 provides a data ready signal.The SPI interface enables the second sequence. simple integration with many embedded processor platforms, Figure 6 includes three single register reads in succession.In as shown in Figure 5(electrical connection)and Table 6(processor this example,the process starts with DIN=0x0400 to request pin descriptions). the contents of the XACCL_OUT register,followed by 0x0600 IO LINES ARE COMPATIBLE WITH 3.3V VDD 3.3V OR 5V LOGIC LEVELS to request the contents of the YACCL_OUT register,and then 0x0800 to request the contents of the ZACCL_OUT register. SYSTEM Full duplex operation enables processors to use the same 16-bit PROCESSOR ④cs ADIS16210 SPI MASTER SPI cycle to read data from DOUT while requesting the next set SCLK ③scLK of data on DIN. MOSI 11 DIN DIN 0x0400 0x0600 0x0800 MISO ②DOUT IRQ ③DHO1 DOUT XACCL_OUT YACCL OUT ZACCL_OUT Figure 6.SPI Read Example Remove R0FE Figure 7 provides an example of four SPI signals when reading Figure 5.Electrical Connection Diagram PROD ID in a repeating pattern. Table 6.Generic Master Processor Pin Names and Functions cs7 Pin Name Function salx厂 SS Slave select IRQ Interrupt request,optional DINDIN=010101100000000=0x5600 MOSI Master output,slave input DOUT 几几Π MISO Master input,slave output D0UT=0011111101011100=0x3F52=16210 SCLK Serial clock Figure 7.SPl Read Example,Second 16-Bit Sequence The ADIS16210 SPI interface supports full duplex serial commu- DEVICE CONFIGURATION nication(simultaneous transmit and receive)and uses the bit The user register map(Table 8)provides a variety of control sequence shown in Figure 9.Table 7 provides a list of the most registers,which enable optimization for specific applications. common settings that initialize the serial port of a processor for the The SPI provides access to these registers,one byte at a time, ADIS16210 SPI interface. using the bit assignments shown in Figure 9.Each register has Table 7.Generic Master Processor SPI Settings 16 bits,where Bits[7:0]represent the lower address and Bits[15:8] Processor Setting Description represent the upper address.Figure 8 displays the SPI signal Master ADIS16210 operates as a slave pattern for writing 0x07 to Address 0x38,which sets the number SCLK Rate≤830kHz Maximum serial clock rate of averages to 128 and the sample rate to 4 SPS. SPI Mode 3 CPOL=1(polarity),CPHA=1(phase) cs MSB-First Mode Bit sequence sckU厂 16-Bit Mode Shift register/data length w冂 DIN=1011100000000111=0xB807,SET AVG_CNTI7:0=0x07 Figure8.Example SPIWrite Pattern c SCLK DIN R/WASASA4 A3A2 A1 A0 DC7 DC6 DCS DC4DC3 DC2 DC1 DCOR/W A6 A5 DOUT D15D14D13D12D11D10D9D8D765D4D3D2D1D0D15D14D13 NOTES 1.DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W =0. 2.WHEN CS IS HIGH,DOUT IS IN A THREE-STATE,HIGH IMPEDANCE MODE,WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. Figure 9.SPI Communication Bit Sequence Rev.A|Page7 of 20
ADIS16210 Rev. A | Page 7 of 20 BASIC OPERATION The ADIS16210 is an autonomous system that requires no user initialization. Upon receiving a valid power supply, it initializes itself and starts sampling, processing, and loading data into the output registers. When using the factory default configuration, DIO1 provides a data ready signal. The SPI interface enables simple integration with many embedded processor platforms, as shown in Figure 5 (electrical connection) and Table 6 (processor pin descriptions). SYSTEM PROCESSOR SPI MASTER ADIS16210 SCLK CS DIN DOUT SCLK SS MOSI MISO 3.3V IRQ DIO1 VDD I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS 14 13 11 12 15 1 2 3 4 5 8 09593-006 Figure 5. Electrical Connection Diagram Table 6. Generic Master Processor Pin Names and Functions Pin Name Function SS Slave select IRQ Interrupt request, optional MOSI Master output, slave input MISO Master input, slave output SCLK Serial clock The ADIS16210 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 9. Table 7 provides a list of the most common settings that initialize the serial port of a processor for the ADIS16210 SPI interface. Table 7. Generic Master Processor SPI Settings Processor Setting Description Master ADIS16210 operates as a slave SCLK Rate ≤ 830 kHz Maximum serial clock rate SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase) MSB-First Mode Bit sequence 16-Bit Mode Shift register/data length READING SENSOR DATA A single register read requires two 16-bit SPI cycles. The first cycle requests the contents of a register using the bit assignments in Figure 9. The register contents then follow on DOUT, during the second sequence. Figure 6 includes three single register reads in succession. In this example, the process starts with DIN = 0x0400 to request the contents of the XACCL_OUT register, followed by 0x0600 to request the contents of the YACCL_OUT register, and then 0x0800 to request the contents of the ZACCL_OUT register. Full duplex operation enables processors to use the same 16-bit SPI cycle to read data from DOUT while requesting the next set of data on DIN. DIN DOUT 0x0400 0x0600 0x0800 XACCL_OUT YACCL_OUT ZACCL_OUT 09593-007 Figure 6. SPI Read Example Remove Figure 7 provides an example of four SPI signals when reading PROD_ID in a repeating pattern. DOUT = 0011 1111 0101 1100 = 0x3F52 = 16210 DIN = 0101 0110 0000 0000 = 0x5600 CS SCLK DIN DOUT 09593-008 Figure 7. SPI Read Example, Second 16-Bit Sequence DEVICE CONFIGURATION The user register map (Table 8) provides a variety of control registers, which enable optimization for specific applications. The SPI provides access to these registers, one byte at a time, using the bit assignments shown in Figure 9. Each register has 16 bits, where Bits[7:0] represent the lower address and Bits[15:8] represent the upper address. Figure 8 displays the SPI signal pattern for writing 0x07 to Address 0x38, which sets the number of averages to 128 and the sample rate to 4 SPS. DIN = 1011 1000 0000 0111 = 0xB807, SET AVG_CNT[7:0] = 0x07 CS SCLK DIN 09593-009 Figure 8. Example SPI Write Pattern 09593-113 R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 R/W D15 D12D13D14 D11 D10 D7D8D9 D6 D3D4D5 D2 D0D1 CS SCLK DIN DOUT A6 A5 D15 D13D14 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. Figure 9. SPI Communication Bit Sequence