OActive-HDL 4.2 (design not loaded)-E: \MY HOLdesignladdersrelVIDL. O X File Edit Search View Design Simulation Tools Help 》x library ieee: use ieee std logic 1164.all: entity ent name 1s port (pl, p2: in std logic; p3: out std logic vector(7 downto 0)): end entname; architecture arch name of ent name is 10 11 component compnane 12 port (pl: in std logic; 13 p2: out std logio): 14 end component d design flow E whdlstandar R eady Ln TT, Col 67 MUMINS
O Active-HDL 4.2 (design not loaded)-E: \MY _HOLdesignladder\srcWVHDL-Ox File Edit Search view Desi gn Simulation Tools Help 》x 16 signal signame1, signame2: std logic: =U 17 for all: compname use entity work. compname(behave); 19 begin 20 Proc name: process(p1, p2, p3) 21 variable varname1, varname2: std logic :=U 22 23 begin 24 signame l < expression after delay; 56 varname1 : expression; 27 procedure call(paraml, param2, par am3); 28 29 wait for delay: d design flow Ewhdlstandar In77,Co167 NUM INS
O Active-HDL 4.2 (design not loaded)-E: \MY _HOLdesignladder\srcWVHDL-Ox File Edit Search view Desi gn Simulation Tools Help 》x 26 27 procedure call(param1, param2, param); 29 wait for delay Wai语句 30 wait until condition: 1 walt: - wazt o2一- later. 32 33 if condition then |F语句 34 sequential statements 35 elsif condition then 36 sequential statements: 37 else 38 sequential statements 39 end if: d design flow Ewhdlstandar In77,Co167 NUM INS
Wait语句 — — later… - - IF语句
O Active-HDL 4.2 (design not loaded)-E: \MY _HOLdesignladder\srcWVHDL-Ox File Edit Search view Desi gn Simulation Tools Help 》x 40 41 Case吕e1 ection 1s case语句 42 when choice1=> 43 sequential statements: 44 when choice choice3=> 45 sequential statements 46 when others = 47 sequential statements; 48 end case 49 50 for i in a range loop -for循环语句 51 sequential statements: 52 end loop 53 d design flow Ewhdlstandar In21,Co167 NUM INS
- - case语句 - - for循环语句
O Active-HDL 4.2 (design not loaded)-E: \MY _HOLdesignladder\srcWVHDL-Ox File Edit Search view Desi gn Simulation Tools Help 》x 54 while condition loop -Whie循环语句 55 sequential statements 56 condition updates: 57 end loop; 89 end process Proc name; conditional signal assignment 60 signame 1 < expr 1 when condition else 61 expr2 62 selected signal assignment 63 with expression select 64 signame2 < x1 when choices 1 5 x2 when choices 66 67 xn when others d design flow Ewhdlstandar In21,Co167 NUM INS
- - while循环语句 -- conditional signal assignment -- selected signal assignment