esTc 设计中 电子设计自动化技术 教师:李平教授(博导) Email: pliQuestc. edu.cn Te:83201794
设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794
esTc 设计中 电子设计自动化技术 补充内容 Model Referencing of Library/Package Implied Process and Explicit Process Combinatorial Process and Sequential Process
设计中心 电子设计自动化技术 补充内容 Model Referencing of Library/Package Implied Process and Explicit Process Combinatorial Process and Sequential Process
esTc 设计中 VHDL VHSIC( Very High Speed Integrated Circuit Hardware Description Language
设计中心 VHDL • VHSIC (Very High Speed Integrated Circuit) • Hardware • Description • Language
VHDL描述的总体结构 Package Generics Entity Architecture Architecture Architecture (Data Flow) (Behavioral) (structural) oncurrentConcurrent Process tatements Statements Sequential Statements
VHDL设计中心 描述的总体结构
esTc 设计中 Behavior Modeling Only the functionality of the circuit, no structure No specific hardware intent For the purpose of synthesis, as well as simulation N1,,,|Nn F in1 THEN ①UT1,,OUTn FOR j IN high DOWNTO low LOOP shft(): =shft() END LOOP out1 < shft AFTER 5ns
设计中心 Behavior Modeling • Only the functionality of the circuit, no structure • No specific hardware intent • For the purpose of synthesis, as well as simulation IN1，…，INn IF in1 THEN OUT1，…，OUTn FOR j IN high DOWNTO low LOOP shft(j) := shft(j); END LOOP; out1 <= shft AFTER 5ns