Step 2: Components of the Datapath a Combinational Elements a Storage Elements Clocking methodology 日209 Chapter4A11 CSE SJTU, 2017
EI209 Chapter 4A.11 CSE, SJTU, 2017 Step 2: Components of the Datapath ❑ Combinational Elements ❑ Storage Elements Clocking methodology
Combinational Logic Elements(Basic Building Blocks) CarryIn 口 Adder 口( Decoder) A 32 Sum outO B 32 Carry …Out1 32 口MUX .sEIn.+ out7 Selec A 32 32 32 口ALU OP A-oN Result 32 B 32 日209 Chapter4A.12 CSE SJTU, 2017
EI209 Chapter 4A.12 CSE, SJTU, 2017 Combinational Logic Elements (Basic Building Blocks) ❑ Adder ❑ MUX ❑ ALU 32 32 A B 32 Sum Carry 32 32 A B 32 Result OP 32 A B 32 Y 32 Selec t Adder MUX ALU CarryIn 3 Decoder out0 out1 out7 out2 (Decoder)
Storage Element: Register(Basic Building Block) Register Write enable N-bit input and output Write Enable input Data in Data out Write enable negated( 0): Data Out will not change asserted (1): Data Out will become Data In Clk 日209 Chapter4A.13 CSE SJTU, 2017
EI209 Chapter 4A.13 CSE, SJTU, 2017 Storage Element: Register (Basic Building Block) ❑ Register - N-bit input and output - Write Enable input Write Enable: - negated (0): Data Out will not change - asserted (1): Data Out will become Data In Clk Data In Write Enable N N Data Out
Storage Element: Register File a Register File consists of 32 registers RWRA RB Write enable TWO 32-bit output busses 早早早 busa and busB bUSA busW One 32-bit input bus: busW 3232-bit 32 32 a Register is selected by Clk Registers bus 32 RA(number) selects the register to put on busA(data) RB(number) selects the register to put on busB(data RW(number) selects the register to be written via busW(data when Write Enable is 1 a Clock input(CLK) The ClK input is a factor oNLY during write operation During read operation, behaves as a combinational logic block Ra or RB valid = busa or bus b valid after access time 日209 Chapter4A.14 CSE SJTU, 2017
EI209 Chapter 4A.14 CSE, SJTU, 2017 Storage Element: Register File ❑ Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW ❑ Register is selected by: RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1 ❑ Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 32 busA 32 busB 5 5 5 RWRA RB 32 32-bit Registers
Storage Element: Idealized Memory Write Enable Address a Memory(idealized One input bus: Data In DataIn DataOut One output bus: Data Out 32 32 Clk a Memory word is selected by Address selects the word to put on Data Out Write Enable= 1: address selects the memory word to be written via the data In bus a Clock input (CLK) The clk input is a factor only during write operation During read operation behaves as a combinational logic block Address valid = Data Out valid after access time 日209 Chapter4A.15 CSE SJTU, 2017
EI209 Chapter 4A.15 CSE, SJTU, 2017 Storage Element: Idealized Memory ❑ Memory (idealized) One input bus: Data In One output bus: Data Out ❑ Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus ❑ Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 32 DataOut Address