Clocking Methodologies a Clocking methodology defines when signals can be read and when they can be written falling(negative) edge clock cycle rising(positive) edge clock rate 1/(clock cycle) e.g., 10 nsec clock cycle 100 MHz clock rate 1 nsec clock cycle =1 GHz clock rate a State element design choices level sensitive latch master-slave and edge-triggered flipflops 日209 Chapter4A.16 CSE SJTU, 2017
EI209 Chapter 4A.16 CSE, SJTU, 2017 Clocking Methodologies ❑ Clocking methodology defines when signals can be read and when they can be written falling (negative) edge rising (positive) edge clock cycle clock rate = 1/(clock cycle) e.g., 10 nsec clock cycle = 100 MHz clock rate 1 nsec clock cycle = 1 GHz clock rate ❑ State element design choices level sensitive latch master-slave and edge-triggered flipflops
Recall: Clocking Methodology Clk Setup Hold Setup Hold Don't Care a Al storage elements are clocked by the same clock edge a Cycle Time =CLK-to-Q+ Longest Delay Path+Setup+Clock Skew 日209 Chapter4A.17 CSE SJTU, 2017
EI209 Chapter 4A.17 CSE, SJTU, 2017 Recall: Clocking Methodology ❑ All storage elements are clocked by the same clock edge ❑ Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clk Don’t Care Setup Hold . . . . . . . . . . . . Setup Hold
Step 3: Assemble DataPath meeting our requirements a Register Transfer Requirements → Datapath assembl a Instruction Fetch a Read Operands and Execute Operation 日209 Chapter4A.18 CSE SJTU, 2017
EI209 Chapter 4A.18 CSE, SJTU, 2017 Step 3: Assemble DataPath meeting our requirements ❑ Register Transfer Requirements Datapath Assembly ❑ Instruction Fetch ❑ Read Operands and Execute Operation