The MiPs Instruction Formats o Al MIPS instructions are 32 bits long the three instruction formats 21 16 R-type rs shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 26 21 16 I-type rs immediate 6 bits 5 bits 5 bits 16 bits J-type 31 26 target address 6 bits 26 bits o The different fields are op: operation of the instruction rs,rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the"op" field address / immediate: address offset or immediate value target address: target address of the jump instruction 日209 Chapter4A.6 CSE SJTU, 2017
EI209 Chapter 4A.6 CSE, SJTU, 2017 The MIPS Instruction Formats ❑ All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type ❑ The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction op target address 31 26 0 6 bits 26 bits op rs rt rd shamt funct 31 26 21 16 11 6 0 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 31 26 21 16 0 6 bits 5 bits 5 bits 16 bits
Logical Register Transfers a rtl gives the meaning of the instructions a All start by fetching the instruction op rs rt rd shamt funct= MEM[ PC] op rs rt Imm16 MEM PC inst Register Transfers ADDU Rrd] <-R[rs]+ rrt PC <-PC +4 SUBU R[rd]<-R[rs-R[rt PC <-PC +4 ORi R[rt]<-R[rs] zero_ext(Imm16 PC <-PC +4 LOAD R[rt]<-MEMI R[rs]+ sign ext(Imm16)]: PC <-PC+4 STORE MEM[ R[s]+ sign ext(mm16)]<-Rrt]; PC <-PC+ 4 BEQ if( r[rs]== Rirt] then PC <-PC 4 +sign ext(Imm16)100 else pc <-PC +4 日209 Chapter4A7 CSE SJTU, 2017
EI209 Chapter 4A.7 CSE, SJTU, 2017 Logical Register Transfers ❑ RTL gives the meaning of the instructions ❑ All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 +sign_ext(Imm16)] || 00 else PC <– PC + 4
Step 1: Requirements of the Instruction Set 口 Memory instruction data a Registers(32×32) read Rs read rt Write rt or rd 口PC 口 Extender a Add and Sub register or extended immediate D Add 4 or extended immediate to pc 日209 Chapter4A.8 CSE SJTU, 2017
EI209 Chapter 4A.8 CSE, SJTU, 2017 Step 1: Requirements of the Instruction Set ❑ Memory instruction & data ❑ Registers (32 x 32) read RS read RT Write RT or RD ❑ PC ❑ Extender ❑ Add and Sub register or extended immediate ❑ Add 4 or extended immediate to PC
Step 1: Requirements of the Instruction Set 口 Memory(MEM) Instructions data (will use one for each: really caches) 口 Registers(R:32X32) Read rs Read rt Write rt orr 口PC a Extender (sign/zero extend) a Add/Sub/ORunit for operation on register(s)or extended immediate a Add 4(+ maybe extended immediate)to PC a Compare if registers equal? 日209 Chapter4A.9 CSE SJTU, 2017
EI209 Chapter 4A.9 CSE, SJTU, 2017 Step 1: Requirements of the Instruction Set ❑ Memory (MEM) Instructions & data (will use one for each: really caches) ❑ Registers (R: 32 x 32) Read rs Read rt Write rt or rd ❑ PC ❑ Extender (sign/zero extend) ❑ Add/Sub/OR unit for operation on register(s) or extended immediate ❑ Add 4 (+ maybe extended immediate) to PC ❑ Compare if registers equal?
Generic Steps of Datapath rd Loc①E rs ALU 0点 Imm 1. Instruction 2. Decode/ 3. EXecute 4. Memory 5. Register Fetch Register Write Read 日209 Chapter4A.10 CSE SJTU, 2017
EI209 Chapter 4A.10 CSE, SJTU, 2017 Generic Steps of Datapath instruction memory +4 rt rs rd registers ALU Data memory imm 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory5. Register Write PC mux