Computer Organization Fa12017 Chapter 4A: The Processor, Part A [Adapted from Computer Organization and Design, 4th Edition, Patterson Hennessy, C 2012, MKI 日209 Chapter4A.1 CSE SJTU, 2017
EI209 Chapter 4A.1 CSE, SJTU, 2017 Computer Organization Fall 2017 Chapter 4A: The Processor, Part A [Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2012, MK]
Review: MIPS(RISC)Design Principles a Simplicity favors regularity fixed size instructions small number of instruction formats opcode always the first 6 bits 口 Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes o Make the common case fast arithmetic operands from the register file(load-store machine allow instructions to contain immediate operands a Good design demands good compromises three instruction formats 日209 Chapter4A2 CSE SJTU, 2017
EI209 Chapter 4A.2 CSE, SJTU, 2017 Review: MIPS (RISC) Design Principles ❑ Simplicity favors regularity fixed size instructions small number of instruction formats opcode always the first 6 bits ❑ Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes ❑ Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands ❑ Good design demands good compromises three instruction formats
The Processor: Datapath Control a Our implementation of the miPs is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beg, j a generic implementation use the program counter(PC)to supply Fetch the instruction address and fetch the =PC+4 instruction from memory(and update the PC) Exec Decode decode the instruction (and read registers) execute the instruction a All instructions(except j)use the ALU after reading the registers How? memory-reference? arithmetic? control flow? 日209 Chapter4A.3 CSE SJTU, 2017
EI209 Chapter 4A.3 CSE, SJTU, 2017 ❑ Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j ❑ Generic implementation use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) decode the instruction (and read registers) execute the instruction ❑ All instructions (except j) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 Exec Decode
Aside: Clocking Methodologies a The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements-a memory element such as a register Edge-triggered-all state changes occur on a clock edge a Typical execution read contents of state elements - send values through combinational logic -> write results to one or more state elements State Combinational State element logic element 2 clock one clock cycle O Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs 日209 Chapter4A.4 CSE SJTU, 2017
EI209 Chapter 4A.4 CSE, SJTU, 2017 Aside: Clocking Methodologies ❑ The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements - a memory element such as a register Edge-triggered – all state changes occur on a clock edge ❑ Typical execution read contents of state elements -> send values through combinational logic -> write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle ❑ Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs
How to Design a Processor: step-by-step o 1. Analyze instruction set = datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISa registers possibly more datapath must support each register transfer a 2. Select set of datapath components and establish clocking methodology a 3. Assemble datapath meeting the requirements a 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 0 5 Assemble the control logic 日209 Chapter4A.5 CSE SJTU, 2017
EI209 Chapter 4A.5 CSE, SJTU, 2017 How to Design a Processor: step-by-step ❑ 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers - possibly more datapath must support each register transfer ❑ 2. Select set of datapath components and establish clocking methodology ❑ 3. Assemble datapath meeting the requirements ❑ 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ❑ 5. Assemble the control logic