a counter with load reset dir (E,g a clock that can be preset Load: for setting output to some value DIR: for up/ down control CE: count or not count control reset 16-bit din( data in) DIR 16-bit CE count output lock VHDL 6. examples of FSM ver. 8a
A counter with load, reset, dir. (E,g a clock that can be preset) • Load: for setting output to some value • DIR: for up/down control • CE: count or not count control VHDL 6. examples of FSM ver.8a 11 16-bit count output Load DIR CE clock reset 16-bit din (data in)
Exercise on 6.2 Synchronous clock counter Advantage: Disadvantage: Asynchronous clock counter Advantage: Disadvantage: Synchronous reset counter How to write a synchronous reset input in VHDL? Asynchronous reset counter How to write an asynchronous reset input in VHDL? VHDL 6. examples of FSM ver. 8a
Exercise on 6.2 • Synchronous clock counter – Advantage:? – Disadvantage:? • Asynchronous clock counter – Advantage:? – Disadvantage:? • Synchronous reset counter – How to write a synchronous reset input in VHDL? • Asynchronous reset counter – How to write an asynchronous reset input in VHDL? VHDL 6. examples of FSM ver.8a 12
RESET=Asynchronous A 4-bit counter reset ibrary IEEE; CLK= Synchronous clock architecture behavioral of test1xa is use IEEE std logic 1164.all use IEEE std logic arith. all begin use IEEE std logic unsigned. all process(clK, rESet begin entity testlxa is port( if reset=1 then count <=0000 4-bit parallel load counter asynchronous reset elsif clk=1 and CLK'event then CL RESET: in STD logic if load=1 then count < din CE, LOAD, DIR: in STD logIC. DIN: in STD LOGIC VECTOR(3 downto O) else if ce=1 then COUNT: inout STD LOGIC VECTOR(3 downto O)); if dir=1 then · end test1xa; COUNT < COUnT +1. else COUNT < COUNT-1 end if end if Counting end if end if: here VHDL 6. examples of FSM ver. 8a end process; · end behaviora
A 4-bit counter • library IEEE; • use IEEE.std_logic_1164.all; • use IEEE.std_logic_arith.all; • use IEEE.std_logic_unsigned.all; • entity test1xa is • port ( • -- 4-bit parallel load counter, asynchronous reset • CL, RESET: in STD_LOGIC; • CE, LOAD, DIR: in STD_LOGIC; • DIN: in STD_LOGIC_VECTOR(3 downto 0); • COUNT: inout STD_LOGIC_VECTOR(3 downto 0)); • end test1xa; • architecture Behavioral of test1xa is • begin • process (CLK, RESET) begin • if RESET='1' then COUNT <= "0000"; • elsif CLK='1' and CLK'event then • if LOAD='1' then COUNT <= DIN; • else if CE='1' then • if DIR='1' then • COUNT <= COUNT + 1; • else • COUNT <= COUNT - 1; • end if; • end if; • end if; • end if; • end process; • end Behavioral; VHDL 6. examples of FSM ver.8a 13 Counting here CLK=Synchronous clock RESET=Asynchronous reset
Simulation result 画吗8 value dh DIN[3: 01 n DIR 田DN[3:0 +COUNT3: 0] 0011 001 0010 XO. VHDL 6. examples of FSM ver. 8
Simulation result • VHDL 6. examples of FSM ver.8a 14
library IEEE;--Vivado 2014 4 &ISEok use IEEEstd logic 1164. all use IEEE std_ logic arith. all use IEEE std logic unsigned. all entity syn counteris CLK: in STD LOGIC RESET CE load, DIR: in STD LOGIC DIN: in std logic r 3 downto O); COUNT: inout std logic vector(3 downto o)) end syn counter; architecture Behavioral of syn_ counter is gin process(reset, clk begin if(reset=1then COUNT <=0000 else if(clk'event and clk= 1) then if(load =1)then COUNT < din; else if(ce=1) the if( dir= 1 )the else count <=count-1; nd if nd if: d if; nd if: end if: ocess end Behavioral VHDL 6. examples of FSM ver. 8a 15
• library IEEE; -- (Vivado 2014.4 &ISE ok) • use IEEE.std_logic_1164.all ; • use IEEE.std_logic_arith.all; • use IEEE.std_logic_unsigned.all ; • entity syn_counteris • port ( • CLK: in STD_LOGIC; • RESET,CE, load, DIR: in STD_LOGIC; • DIN: in std_logic_vector(3 downto 0); • COUNT: inoutstd_logic_vector(3 downto 0)); • end syn_counter; • architecture Behavioral of syn_counter is • begin • process( reset, clk) begin • if(reset = '1') then COUNT <= "0000"; • else • if(clk'event and clk = '1') then • if(load = '1') then COUNT <= din; • else • if(ce = '1') then • if( dir = '1') then • count <= count + 1; • else • count <= count -1; • end if; • end if; • end if; • end if; • end if; • end process; • end Behavioral; VHDL 6. examples of FSM ver.8a 15