library IEEE; -(vivado 2014 34 ok) use IEEE std logic_1164.all; entity asyn_ counter is port( clk: in std logic reset: in std logic counto, count1, count2, count3: inout std logic); end asyn counter; architecture Behavioral of asyn counter is process(reset, clk, counto, count1, count2 )begin if reset =1 then counto<=0: count1<=0 count2<=0; count3<= 0 else if(rising_edge(clk) then counto < not counto; d if if(rising_edge(counto)) then count1 < not count 1 nd if; if(rising_edge(count 1 )) then count2<= not count 2: end if: if(rising_edge count2 ) then count3<= not count3: end if: end if: end process; end behavioral: VHDL 6. examples of FSM ver. 8a
• library IEEE; --(vivado 2014.34 ok) • use IEEE.std_logic_1164.all; • entity asyn_counter is • port( clk: in std_logic; • reset: in std_logic; • count0,count1, count2, count3: inout std_logic); • end asyn_counter; • architecture Behavioral of asyn_counter is • begin • process(reset, clk, count0, count1, count2) begin • if reset ='1' then • count0<= '0'; count1<= '0'; • count2<= '0'; count3<= '0'; • else • if(rising_edge(clk)) then count0 <= not count0; • end if; • if(rising_edge(count0)) then count1 <= not count1; • end if; • if(rising_edge(count1)) then count2<= not count2; • end if; • if(rising_edge(count2)) then count3<= not count3; • end if; • end if; • end process; • end Behavioral; VHDL 6. examples of FSM ver.8a 6
Exercise on 6.1, 4-bit Asyn Student ID Clock Counter plot count and Name Date: check delay (Submit this at the end of the lecture Write the port declaration Plot Q(1),Q(2),Q 3 including delays Count(o) Count(1) Count(2) Count(3) D(2 D(3) FF 少FF 少FF PFF cloc k ck'to(0)ck" Q(ck" TQ(2)ck"TQ(3) δt= time delay at one ff reset k CIoc Q(0)-t Q(1) Q(2) VHDL 6. examples of FSM ver. 8a
Exercise on 6.1, 4-bit Asyn. Clock Counter. Plot count, and check delay • Write the port declaration. • Plot Q(1),Q(2),Q(3) including delays VHDL 6. examples of FSM ver.8a 7 FF FF FF FF clock Count(0) Count(1) Count(2) Count(3) reset clock Q(0) Q(1) Q(2) Q(3) t= time delay at one FF ck Q(0) ck Q(1)ck Q(2) ck Q(3) D(0) D(1) D(2) D(3) Student ID: __________________ Name: ______________________ Date:_______________ (Submit this at the end of the lecture.) t
Simulation result 5us 10us 15us 唱 threet ouro count1 品 count2 COunt3 VHDL 6. examples of FSM ver. 8a
Simulation result • VHDL 6. examples of FSM ver.8a 8
Synchronous clock counter design More difficult to design Less delay at outputs( more precise VHDL 6. examples of FSM ver. 8a
Synchronous clock counter design • More difficult to design • Less delay at outputs (more precise) VHDL 6. examples of FSM ver.8a 9
4-bit synchronous counter More complicated than asynchronous design fromhttp://web.cs.munca/paul/cs3724/material/web/notes/img191.png F Clock VHDL 6. examples of FSM ver. 8a
4-bit synchronous counter • More complicated than asynchronous design • from http://web.cs.mun.ca/~paul/cs3724/material/web/notes/img191.png VHDL 6. examples of FSM ver.8a 10