Chapter 6 Examples of finite State machines (FSMS) Counters and pattern generators VHDL 6. examples of FSM ver. 8a
Chapter 6 Examples of Finite State Machines (FSMs) Counters and pattern generators VHDL 6. examples of FSM ver.8a 1
Counters and pattern generators Up/down counters: generate a sequence of gradually increasing or decreasing counting patterns according to the clock and inputs (E.g. digital clock, 1, 2, 3, 4 Pattern generators: generate any patterns of finite states. Use state diagrams to design. ( E.g traffic light, red, green, yellow. VHDL 6. examples of FSM ver. 8a
Counters and pattern generators • Up/down counters: generate a sequence of gradually increasing or decreasing counting patterns according to the clock and inputs. (E.g. digital clock, 1,2,3,4..) • Pattern generators: generate any patterns of finite states. Use state diagrams to design. (E.g. traffic light,red,green, yellow..) VHDL 6. examples of FSM ver.8a 2
Up/down counters are FSms Asyn. clock -more delay among outputs, less logic the output of one state register is the clock of another state register Syn clock -less delay among outputs more logic all clock inputs of state registers (flip-lops are connected Examples here are all Moore machines (output depends on state registers. VHDL 6. examples of FSM ver. 8a
Up/down counters are FSMs • Asyn.clock -more delay among outputs, less logic – the output of one state register is the clock of another state register. • Syn. clock -less delay among outputs, more logic – all clock inputs of state registers (flip-lops) are connected. • Examples here are all Moore machines (output depends on state registers.) VHDL 6. examples of FSM ver.8a 3
Two design methods Asynchronous clock design Easier to design More delay at outputs Synchronous clock design More complex Less time delay at outputs VHDL 6. examples of FSM ver. 8a
Two design methods • Asynchronous clock design – Easier to design – More delay at outputs • Synchronous clock design – More complex – Less time delay at outputs VHDL 6. examples of FSM ver.8a 4
4-bit asynchronous clock down counter(Moore) CLK in STD logic: RESET in STD logiC: CoUNTO, CoUNT1, CoUNT2, COUNT3: inout STD LOGIC; architecture Behavioral of asyn_counter is_ Asynchronous clocks process(reset, clk, counfo, count1, count2)begin if reset= 1' then Each line is countO<=0 count1<=0 an Flip-Flop count2<0 count3<=0 else if(rising_edge(clk ))then counto not counto end if if(rising_edge(counto))then count1 < not count1 ena if(rising_edge(count1 ))then count2< not count2 end if eage( coun nt2)then count3<= not count3 if nd if. end process A 4-BIT DOWN COUNTER end behavioral VHDL 6. examples of FSM ver. 8a
4-bit Asynchronous clock down counter (Moore) CLK: in STD_LOGIC; RESET: in STD_LOGIC; COUNT0, COUNT1 , COUNT2 , COUNT3 : inout STD_LOGIC; VHDL 6. examples of FSM ver.8a 5 Each line is an Flip-Flop Asynchronous clocks A 4-bit down counter