Pattern generators (finite state machines Generate any pattern you desire E.g. CPU Memory controller etc VHDL 6. examples of FSM ver. 8a
Pattern generators (finite state machines) • Generate any pattern you desire. • E.g. CPU, • Memory controller etc. VHDL 6. examples of FSM ver.8a 16
Pattern generators Irregular pattern counter examples: traffic light, memory read/ write patterns The control unit of a computer is a pattern generator. Or the whole digital computer is a pattern generator counting according to the clock and inputs keyboard, memory, disk etc. VHDL 6. examples of FSM ver. 8a
Pattern generators • Irregular pattern counter examples: traffic light, memory read/write patterns. • The control unit of a computer is a pattern generator. • Or the whole digital computer is a pattern generator counting according to the clock and inputs (keyboard, memory, disk etc.) VHDL 6. examples of FSM ver.8a 17
Binary and one-hot encoding for state machine design Binary encoding using n flip-flops to represent 2 states Use less flip-flops but more combinational logics One-hot encoding Using N flip-flops for n states Use more flip-lops but less combination logic · Xilinx default is one-hot. choose at x|L|NⅩ foundation project manager> synthesis options http://www.xilinx.com/itp/xilinx4/data/docs/sim/vte x9. html VHDL 6. examples of FSM ver. 8a 18
Binary and one-hot encoding for state machine design. • Binary encoding: – using N flip-flops to represent 2N states. – Use less flip-flops but more combinational logics • One-hot encoding: – Using N flip-flops for N states. – Use more flip-lops but less combination logic. • Xilinx default is one-hot. choose at XILINX foundation_project_ manager→ synthesis → options. • http://www.xilinx.com/itp/xilinx4/data/docs/sim/vte x9.html VHDL 6. examples of FSM ver.8a 18
Change fsm coding styles in Xilinx - ISE n Implementation view, right click Synthesize, choose design goals ocesses. traffic-bghtA Desian Goals and Strategies Strategy poperty semas 国 Vew Command line Log Fle roperty Name Current Value In Strategy Strategy Value 国 View HDL Instantiation Tempate 3与 血油 Netist hierarch As Optimzed口 Generate Ril schematc Yes : tO Implement Desian 3则g据图将面刻 Herarchy Separator Bus De mter d Vew RTL Run Case G/TAcea3430口0 ab5tsMoest R) Check Sy Rerun b 富国动尴图 HDL INI Fle pO Transate 的的省图情能德 Verilog 2001 Verilog Indude Directories Generics Parameters Verilog Macros Farce Process Upto-Date Other XST Command LIne opt Implement Top Module Safe Implementation 口□口□口口 a Pocess Properties Mux Extraction Choose Tune the coding style Edit Setting VHDL 6. examples of FSM Or keep as default
Change FSM coding styles in Xilinx-ISE • In Implementation view, right click Synthesize, choose Design goals… » VHDL 6. examples of FSM ver.8a 19 Choose Edit Setting Tune the coding style. Or keep as default
EXercise 6.3, State concepts How many states can a 4-bit counter have? How many bits for the state registers using binary encoding are required if you need 4 states? 9 states? 21 states? Repeat the above question if you use one-hot encoding. VHDL 6. examples of FSM ver. 8a
Exercise 6.3, State concepts • How many states can a 4-bit counter have? • How many bits for the state registers (using binary encoding) are required if you need – 4 states? – 9 states? – 21 states? • Repeat the above question if you use one-hot encoding. VHDL 6. examples of FSM ver.8a 20