process(selr en) begin y<="11111111"; if(en=1i) then case sel is when"000"=>y(0)<='0 hen"001"=>y(1)<=10 when"010"=>y(2)<="0 when"011"=>y(3)<=0 hen"100"=>y(4)<=10 when"101"=>y(5)<="0 hen"110”=>y(6)<=0’;译码输 When"111"=>y(7)<="0 When others=>null 出低有 end case 效 end if end processi end behavior
11 译码输 出低有 效
方法4:使用条件赋值语句 library ieee use ieee std logic 1164.alli entity dec is port(sel: in std logic vector(2 downto 0) en: in std logici out std logic vector(7 downto 0))i end dec: architecture behavior of dec is begin (0)<=0 when (en=1 and sel=000")else'1' y(1)<=!0!when(en=!1 and se1="001")e1se!1 y(2)<=0 when (en=1 and sel=010")else'1'i y(3)<=0 when (en=1 and sel=011")else'1 y(4)<='0when(en=1! and se1="100")e1se11; y(5 <=0 when (en=1 and sel=101)else!1 y(6)<=0 when (en='1 and sel=110)else'1 on y(7)<=0 when (en='1, and sel="111")else'1'i d behavior 12
12 方法4：使用条件赋值语句
3-8译码器仿真结果: i MAX+plus II -h: \vhdl intro app\e_\dec-[dec scf- Waveform Editor] □问 MAX+plus II File Edit View Node Assign Utilities Options window Help 口哆闆舀幽回△國囫郾感国国為圖亟武魯雷眼 A Ref: 0.Ons 卜Time:990ns Interval 999ns 0. Ons Name Value 1000ns 200Ons 300Ons 400Ons 5000ns 600 Ons 7000ns 800Ons 900Ons 1 DO 3 4 y654 11111110 译码输出 低有效
13 3-8译码器仿真结果： 译码输出 低有效
4、加法器 带进位的4位加法器符号如下 ADDER4 a[··9sun[·· b··1 七 C n Sum(i)=a()b(i)⊕cin C(i+1)=a(i)b(i)+(a()+b()c()
14 4、加法器 带进位的 4位加法器符号如下： Sum(i) = a(i) b(i) cin C(i+1) = a(i) b(i) +((a(i) + b(i) ) c(i)
方法1:用for-loop语句实现 library ieee useless·std1og主c1164.a11; entity adder is port(a, b: in sta logic vector (3 downto o)i C主n:1ns七d1○gic; sum: out sta logic vector (3 downto O) count: out std logic)i end adders archi tecture behavior of adder is signal c: std logic vector(4 downto o)i beg n process(a b, cin, c begin C(0)<=Cin; for i ir0to31。op sum(i)<=a(i)xor b(i)xor c(i)i c(i +l)<=(a(i) and b(i)) or (c(i) and(a(i) or b(i)))i end loop count<=c(4)i end processi end behavior 15
15 方法1：用for – loop语句实现