方法3:利用条件赋值语句 architecture behavior of priority is begin vec <=111 when y7=1 else 110 when y6=else 4101” when y5=1else 100 when y4=else 011” when y3=1'else 010 when y2=else 001 when y1=else 0002 when y0= 1'else XXX” end behavior
6 方法3：利用条件赋值语句 architecture behavior of priority is begin vec <= “111” when y7 = ‘1’ else “110” when y6 = ‘1’ else “101” when y5 = ‘1’ else “100” when y4 = ‘1’ else “011” when y3 = ‘1’ else “010” when y2 = ‘1’ else “001” when y1 = ‘1’ else “000” when y0 = ‘1’ else “XXX”; end behavior;
3、译码器 译码器是编码器的逆过程。如3-8译码器 sel=000Y=00000001 Sel=001Y=00000010 DEC sel=010Y=00000 seL[2。]y[7。 sel=011Y=00001000 sel=100Y=00010000 sel=101Y=00100000 sel=110Y=01000000 sel=111Y=10000000
7 3、译码器 译码器是编码器的逆过程。如 3-8 译码器： sel=000 Y=00000001 sel =001 Y=00000010 sel =010 Y=00000100 sel =011 Y=00001000 sel =100 Y=00010000 sel =101 Y=00100000 sel =110 Y=01000000 sel =111 Y=10000000
方法1:使用逻辑左移运算符 library leee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin outp<=00000001 sll(conv integer(inp)) end rtl
8 方法1：使用逻辑左移运算符 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin outp<=“00000001” sll(conv_integer(inp)); end rtl;
方法2:使用 processi语句 library ieee use ieee std logic 1164. all use ieee std logic unsigned. all entity decoder is port(inp: in std logic vector(2 downto 0 outp: out std logic vector(7 downto O)) end decoder architecture rtl of decoder is begin process(inp) begin outp<=(others=>0) outp( conv integer(inp)-="1 end process end rtl
9 方法2：使用process语句 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(inp : in std_logic_vector(2 downto 0); outp : out std_logic_vector(7 downto 0)); end decoder; architecture rtl of decoder is begin process(inp) begin outp<=(others=>’0’); outp(conv_integer(inp))<=‘1’; end process; end rtl;
方法3:使用case语句实现。 library ieee; use ieee std logic 1164.all entity dec is port (sel: in std logic vector(2 downto 0)i en: in std logici out std logic vector(7 downto 0) end dec: architecture behavior of dec is begi
10 方法3：使用 case 语句实现