esTc 设计中 Operator Overloading Function/Package Packages that define these operator overloading functions can be found in the LIBRARY EEE For example, the package std logic unsigned defines some of the following functions package std logic unsigned is function+(L: STD LOGIC VECTOR; R: STD LOGIC VECTOR) return STD LOGIC VECTOR; 三 function“+生 STD:LOGIC VECTOR:R: INTEGER return STD LOGIC VECTOR function"+"(L INTEGER R: STD LOGIC VEC TOR)return STD LOGIC VECTOR unction+(L: STD LOGIC VECTOR: R: STD LOGIC) retum STD LOGIC VECTOR function"+(E STD LOGIC, R: STD LOGIC VECTOR)return STD LOGIC VECTOR; function "(L: STD LOGIC VECTOR: R: STD LOGIC VECTOR)return STD LOGIC VECTOR function"-(L: STD LOGIC VECTOR; R: INTEGER) return STD LOGIC VECTOR; function"-"(L: INTEGER;R STD LOGIC VECTOR return STD LOGIC VECTOR, function"-(L: STD LOGIC VECTOR; R: STD LOGIC) return STD LOGIC VECTOR; function"-(L: STD LOGIC; R:STD EOGIC-VECTOR return STD LOGIC VECTOR
设计中心 Operator Overloading Function/Package • Packages that define these operator overloading functions can be found in the LIBRARY IEEE. • For example, the package std_logic_unsigned defines some of the following functions package std_logic_unsigned is function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR
esTc 设计中 Use of Operator Overloading Include these statements LIBRARY ieee at the beginning of a USE ieee std logic 1164. all; design file USE ieee std logic unsigned. all ENTITY overload Is PORT(a: IN STD LOGIC VECTOR 3 downto O b: IN STD LOGIC VECtOR 3 downto O); sum: OUT STD LOGIC VECTOR (4 downto 0) END overload
设计中心 Use of Operator Overloading LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY overload IS PORT ( a : IN STD_LOGIC_VECTOR (3 downto 0); b : IN STD_LOGIC_VECTOR (3 downto 0); sum : OUT STD_LOGIC_VECTOR (4 downto 0)); END overload; Include these statements at the beginning of a design file