esTc 设计中 Recall: VHDL implicit library(built-in Library STD Types defined in the Standard package -BIT, BOOLEAN, INTEGER Note: Items in this package do not need to be referenced, they are implied Q: Library ieeE do need to be referenced, whenever?
设计中心 Recall: VHDL implicit library (built-in) – Library STD • Types defined in the Standard package: – BIT, BOOLEAN, INTEGER Note: Items in this package do not need to be referenced, they are implied. Q: Library IEEE do need to be referenced, whenever?
esTc 设计中 Libraries LIBRARY EEER Contains the following packages std logic 1164 (std logic types related functions o std_logic_arith(arithmetic functions) std logic signed(signed arithmetic functions) std logic_ unsigned(unsigned arithmetic functions)
设计中心 Libraries LIBRARY IEEE; – Contains the following packages: • std_logic_1164 (std_logic types & related functions) • std_logic_arith (arithmetic functions) • std_logic_signed (signed arithmetic functions) • std_logic_unsigned (unsigned arithmetic functions)
esTc 设计中 EEE库的包集合内容 包集合 STD LOG|C_1164 STD_LOG| C_ARITH STD_LOGIC_ UNSIGNED STD_LOGIC + " ABS, <, <= ConV_INTEGER(A) STD ULOGIC > >=,=,= SHL STD_LOGIC_VECTOR ConV_STD_LOGIC V 包含内容 Rising edge ECTOR(A位长) ConV_INTEGER(A) Falling_edge To_STDLOGICVECTOR(A 了卩To_ BITVECTOR(A) To_STDLOGIC(A) STD LOGIC TO_BIT(A) And,or,…,…
设计中心 IEEE库的包集合内容 包集合 STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_UNSIGNED 包 含 内 容 STD_LOGIC STD_ULOGIC STD_LOGIC_VECTOR Rising_edge Falling_edge To_STDLOGICVECTOR(A) To_BITVECTOR(A) To_STDLOGIC(A) TO_BIT(A) And, or, … … +, -, *, ABS, <, <=, >, >=, =, /=, SHL Conv_STD_LOGIC_V ECTOR(A,位长) Conv_INTEGER(A) Conv_INTEGER(A)
esTc 设计中 Arithmetic Function ENTITY opr Is PORT(a, IN INTEGER RANGE 0 TO 16 b, NINTEGER RANGE 0 TO 16 sum: OUT INTEGER RANGE 0 TO 32); END opr; ARCHITECTURE example OF opr IS BEGIN The VHDL compiler can adder_body: PROCESS (a, b) understand this BEGIN operation sum <=a+ b because an arithmetic END PROCESS adder_body, operation is defined for END example the built-in data type INTEGER
设计中心 Arithmetic Function ENTITY opr IS PORT ( a : IN INTEGER RANGE 0 TO 16; b : IN INTEGER RANGE 0 TO 16; sum : OUT INTEGER RANGE 0 TO 32); END opr; ARCHITECTURE example OF opr IS BEGIN adder_body:PROCESS (a, b) BEGIN sum <= a + b; END PROCESS adder_body; END example; The VHDL compiler can understand this operation because an arithmetic operation is defined for the built-in data type INTEGER
esTc 设计中 Operator Overloading How do you use Arithmetic Boolean functions with other data types? Operator Overloading-defining Arithmetic Boolean functions with other data types
设计中心 Operator Overloading • How do you use Arithmetic & Boolean functions with other data types? – Operator Overloading - defining Arithmetic & Boolean functions with other data types