esTc 设计中 Signal VS Variable
设计中心 Signal vs Variable
esTc 设计中 Signal vs Variable Signal Assignment(=) receive the assign value after a period of time Variable Assignment happens immediately when the statement is executed, no delay(=)
设计中心 Signal vs Variable • Signal Assignment (<=) – receive the assign value after a period of time • Variable Assignment – happens immediately when the statement is executed, no delay (: =)
esTc 设计中 EXample 三 LIBRARYIEEE; case muxval is EUSE IEEE STD LOGIC 1164ALL. ENTITY mux Is when0≈q<=i0; E PORT(10, il, 12, 13, a, b: IN STD LOGIC when1→>q<=il; 入 9 OUT STD LOGIC) when2→>q<=i2 ND mux; when 3=> g<=i q 13 when others => null: aRCHItECTURE body mux OF mux 4 IS end case: signal muxval: integer end process BEGIN process(i0, 11, 12, 13, a, b) END body mux; begin 。P0饥机 muxval <=0; if (a='1)then pnoULUUU L muxval<= muxval+ 1: FabD3 end if; Qx 8380800808383888380888080830800808080808083838888030808008K if (b=1)then muxval < muxval+2: end if; Why 299?
设计中心 Example LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS signal muxval : integer; BEGIN process(i0,i1,i2,i3,a,b) begin muxval <= 0; if (a = '1') then muxval <= muxval + 1; end if; if (b = '1') then muxval <= muxval + 2; end if; case muxval is when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case; end process; END body_mux4; Why ????
esTc 设计中 FLIBRARYIEEE case muxval is USE IEEE STD LOGIC 1164ALL: when0→>q<=i0; ENTITY mux IS ;。1, a when 1→>q<=il; PORT (O, 11, 12, 13, a, b: IN STD LOGIC, when2→>q<=i2; 9: OUT STD LOGIC) 三 END mux4: when3→>q<=i3; when others = null; ARCHITECTURE body mux4 OF mux Is end case, BEGIN end process; process(i0,11, 12, 13, a, b) End body mux; variable muxval integer Name: Value: I 100 ns 20 ns 300 ns 400 ns 500 Ons 600 Ons 700 ns 800,0r begin mural :=O if(a='1)then p-ll o JUL muxval:= muxval+ 1 end ifa if (b=l)then muxval: =muxval+ 2; end if:
设计中心 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS BEGIN process(i0,i1,i2,i3,a,b) variable muxval : integer; begin muxval := 0; if (a = '1') then muxval := muxval + 1; end if; if (b = '1') then muxval := muxval + 2; end if; case muxval is when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case; end process; END body_mux4;
esTc 设计中 Key points to remember Function Variables represent local storage variables is updated immediately the updated value can be used later in the model for further computations Signals represent circuit interconnect · Place of declare -Variables allow within Process structure -Signal: allow within Architecture structure
设计中心 Key points to remember • Function – Variables represent local storage • Variables is updated immediately – the updated value can be used later in the model for further computations – Signals represent circuit interconnect • Place of Declare – Variables : allow within Process structure – Signal : allow within Architecture structure