Chinaopub.com 第1验证123 载 wire slave Clk parameter toN= 2, toFF =3, tPHASE DELAY= 1; #toN Master Clk= 0 e toFF Master cik assign井 t PHASE DELAY S1aveC1片 Master Clk endmodule Master Clock 113测试验证程序实例 11.3.1解码器 下面是2-4解码器和它的测试验证程序。任何时候只要输入或输出信号的值发生变化,输 信号的值都会被显示输出 module Dec2x4(A, B, Enable, e input output [0:32 wire Abar, Bbar not#(1,2) V1(Bar, B)i No(Z [0], Enable, Abar, Bbar 1(z[1],Enab1e,A上 N2(Z[2], Enable, A, bbar, N3(Z[3,Enable, A, B wire [0:3 Dz/ //被测试的模块: Dec2x4 Di(Da, Db, Dena, DEi
w i r e S l a v e _ C l k ; p a r a m e t e r t O N = 2, tOFF = 3, tPHASE_DELAY = 1; a l w a y s b e g i n #tON Master_Clk= 0; #tOFF Master_Clk= 1; e n d assign #tPHASE_DELAY Slave_Clk = M a s t e r _ C l k; e n d m o d u l e 图11-8 相移时钟 11.3 测试验证程序实例 11.3.1 解码器 下面是2 - 4解码器和它的测试验证程序。任何时候只要输入或输出信号的值发生变化，输 出信号的值都会被显示输出。 ` t i m e s c a l e 1ns / 1ns m o d u l e D e c 2 x 4 (A, B, Enable, Z) ; i n p u t A, B, Enable; o u t p u t [0:3] Z; w i r e Abar, Bbar; n o t # (1, 2) V0 (Abar, A), V1 (Bar, B) ; n a n d # (4, 3) N0 (Z [0], Enable, Abar, Bbar) , N1 (Z [1], Enable, Abar, B) , N2 (Z [2], Enable, A, Bbar) , N3 (Z [3], Enable, A, B) , e n d m o d u l e m o d u l e D e c _ T e s t ; r e g Da, Db, Dena; w i r e [0:3] D z ; / /被测试的模块： Dec2x4 D1 (Da, Db, Dena, Dz) ; 第11章 验 证 123 下载
124D)硬件述语言 Chinapub.com 下载 //产生输入激励 in⊥七ia1 begin Dena #10 Dena =1 #10Da #10Db=1 #10Db=0; #10 sstop //输出模拟结果: e( Dena or Da。 r Db or Dz) disp⊥ay(" At time各t, input⊥s旨b詈bb, output⊥s,b stime, Da, Db, Dena, Dk; endmodule 下面是测试模块执行时产生的输出。 At time output is 1111 t time 10, input is 001, output is 1111 At time 13, input is 00l, output is 0111 At time 20, input is 101, output is 0111 At time 23, input is 101, output is 0101 at time 26, input is 101, output is 1101 At time 30, input is 1ll, output is 1101 At time .t time 36, input is 1ll, output is 1110 At time 40, input is 0ll, output is 1110 At time tis011,。 utput is1011 At time 50, input is 001, output is 1011 At time 54, input is 001, output is 0111 1132触发器 下例是主从D触发器及其测试模块 module MSDFF (D, C, Q, obar output o, obar NT1(NotD, D) NT2(NotC, C) NT3(NotY, Y) D, g ND3(￥,D1,Yba↓
/ /产生输入激励： i n i t i a l b e g i n Dena = 0; Da = 0; D b = 0; #10 Dena = 1; #10 Da = 1; #10 D b = 1; #10 D a = 0; #10 D b = 0; #10 $stop; e n d / /输出模拟结果： a l w a y s @ (Dena o r Da o r Db or D z) $d i s p l a y ("At time %t, input is %b%b%b, output is %b" , $ t i m e , Da, Db, Dena, Dz) ; e n d m o d u l e 下面是测试模块执行时产生的输出。 At time 4, input is 000, output is 1111 At time 10, input is 001, output is 1111 At time 13, input is 001, output is 0111 At time 20, input is 101, output is 0111 At time 23, input is 101, output is 0101 At time 26, input is 101, output is 1101 At time 30, input is 111, output is 1101 At time 33, input is 111, output is 1100 At time 36, input is 111, output is 1110 At time 40, input is 011, output is 1110 At time 44, input is 011, output is 1011 At time 50, input is 001, output is 1011 At time 54, input is 001, output is 0111 11.3.2 触发器 下例是主从D触发器及其测试模块。 m o d u l e MSDFF (D, C, Q, Qbar) ; i n p u t D, C; o u t p u t Q, Qbar; not NT1 (NotD, D)， NT2 (NotC, C)， NT3 (NotY, Y)； nand N D 1 (D1, D, C) , N D 2 (D2, C, NotD) , N D 3 (Y, D1, Ybar) , 124 Verilog HDL 硬件描述语言 下载