® 嵌入式处理器体系结构 李曦 llxx@ustc.edu.cn
嵌入式处理器体系结构 李曦 llxx@ustc.edu.cn
内容提要 ® ·嵌入式处理器概述（实例） ·通用处理器体系结构 CISC RISC ·嵌入式处理器 ·VO系统 一中断 -DMA
内容提要 • 嵌入式处理器概述（实例） • 通用处理器体系结构 – CISC – RISC • 嵌入式处理器 • I/O系统 – 中断 – DMA
Stanford STARMAC Project Low Level Carbon Fiber Control Processor Tubing Robostix Fiberglass High Level Honeycomb Control Processor Plastic Tube Stargate SBC Straps or PC/104 GPS Superstar ll Sonic Ranger Brushless DC Motors SRF08 Axi2208/26 Inertial Measurement Unit (IMU) Electronic Speed 3DMG-X1 Battery Controller Lithium Phoenix 25 LIDAR Stereo Vision Polymer Hokuyo Videre Systems URG-04LX Small Vision System
Stanford STARMAC Project
四旋翼飞控：STARMAC architecture LIDAR RS232 URG-04LX 115 kbps 10 Hz ranges PC/104 WiFi Pentium M USB 2 Stereo Cam 802.11g+ Firewire 1GB RAM,1.8GHz 480 Mbps s 54 Mbps Videre STOC RS232 Est.control 30fps320x240 480 Mbps 年中年年年年年年年 年年年年年年车金年年年年年年年年年出年年。。。年年年年年年 GPS UART Superstar Il 19.2 kbps Stargate 1.0 WiFi 10H2 Intel PXA255 CF UART 64MB RAM.400MHz 802.11b 100 Mbps S5 Mbps IMU 115 Kbps UART Supervisor,GPS 3DMG-X1 UART Robostix 76 or 100 Hz 115 kbps Atmega128 Low level control Ranger PPM SRF08 400 kbps 100Hz 13 Hz Altitude Analog Ranger Beacon Mini-AE ESC Motors Timing/ Tracker/DTS 10-50 Hz Altitude Analog Phoenix-25.Axi 2208/26 1 Hz
四旋翼飞控：STARMAC architecture
Typical Architecture for RTS USTC 嵌入式系统虽然复杂，但通用处理器的设计经验会有很大帮助 Peripheral Bus DEBUG Port Non-volatile memory Custom Devices ·EPROM,FLASH,DISK ·ASIC Hybrid ·FPGA Microprocessor ·PAL 4.8.16.32.4 bit bus ·CISc,RISC,DSP Standard Devices Integrated peripherals Volatile Memory ·Debug/Test Port 1/0 Ports ·DRAM,SRAM ·Caches Peripheral Controllers ·Pipeline Hybrid Multiprocessing Systems Communication Devices ·Ethemet .RS-232 ·scsl ·Centronics System Clocks Proprietary RTC circuitry Software ·System clocks ·Application Code Integrated in uC ·Driver Code/BIOS ·Imported/Exported Microprocessor Bus Real Time Operating System ·Custom User Interface ·PCI Communications Protocol Stacks ·VME .C.C++,Assembly Language ·P℃-102 ·Legacy Code llxx@ustc.edu.cn 5/87
Typical Architecture for RTS llxx@ustc.edu.cn 5/87