Conventional Design Flow Funct. Spec RTL Behar. Simul Logic Synth Stat. Wire model Front-end Gate-level Net Gate-Lev Sim Back-end floorplanning Parasitic Extrac Place route Layout Slides courtesy A Nardi, UC Berkeley
6 Conventional Design Flow Funct. Spec Logic Synth. Gate-level Net. RTL Layout Floorplanning Place & Route Front-end Back-end Behav. Simul. Gate-Lev. Sim. Stat. Wire Model Parasitic Extrac. Slides courtesy A. Nardi, UC Berkeley
From electro-magnetic analysis to circuit simulation Parasitic extraction Electromagnetic analysis Filament Panel with 0 with uniform uniform charge current Model order Thousands ofr l, c reduction Reduced circuit
7 From electro-magnetic analysis to circuit simulation Parasitic extraction / Electromagnetic analysis Thousands of R, L, C Filament with uniform current Panel with uniform charge Model order reduction Reduced circuit
Challenges for parasitic extraction ■ Parasitic Extraction DAs design get larger, and process geometries smaller than 0.35um, the impact of wire resistance, capacitance and inductance(aka parasitics) becomes significant a Give rise to a whole set of signal integrity issues a Challenge o Large run time involved(trade-off for different levels of accuracy) a Fast computational methods with desirable accuracy
8 Challenges for parasitic extraction ◼ Parasitic Extraction As design get larger, and process geometries smaller than 0.35m, the impact of wire resistance, capacitance and inductance (aka parasitics) becomes significant Give rise to a whole set of signal integrity issues ◼ Challenge Large run time involved (trade-off for different levels of accuracy) Fast computational methods with desirable accuracy
Resistance extraction
9 Resistance Extraction
Outline a Introduction to parasitic extraction Resistance extraction a Problem formulation D EXtraction techniques Numerical techniques a Other issues a Capacitance extraction nductance and rlc extraction 10
10 Outline ◼ Introduction to parasitic extraction ◼ Resistance extraction Problem formulation Extraction techniques Numerical techniques Other issues ◼ Capacitance extraction ◼ Inductance and RLC extraction