1.2 Processor Registers (4/4) Control and status registers Program Counter(PC) Contains the address of an instruction to be fetched Instruction Register(Ir Contains the instruction most recently fetched Program Status Word(PSW) Condition codes [more detail next Other state-related bits such as. Interrupt enable/disable Supervisor/user mode
1.2 Processor Registers(4/4) • Control and Status Registers • Program Counter (PC) • Contains the address of an instruction to be fetched • Instruction Register (IR) • Contains the instruction most recently fetched • Program Status Word (PSW) • Condition codes [more detail next] • Other state-related bits, such as: • Interrupt enable/disable • Supervisor/user mode • … … 11
Chapterol Computer system overview ·1.0 Intro ·1.1 Basic e| ements 1.2 Processor registers 1.3 Instruction execution 1.4 Interrupts 1.5 The memory hierarchy ·1.6 Cache Memory 1.7I0 Communication Techniques 1. 8 Evolution of Microprocessor
Chapter01 Computer System Overview • 1.0 Intro • 1.1 Basic Elements • 1.2 Processor Registers • 1.3 Instruction Execution • 1.4 Interrupts • 1.5 The Memory Hierarchy • 1.6 Cache Memory • 1.7 I/O Communication Techniques • 1.8 Evolution of Microprocessor 12
1.3 Instruction Execution (1/9) Program in memory Instruction 1 Instruction n Program 1 PC data 1 R data n R CPU M
1.3 Instruction Execution (1/9) • Program in memory CPU PC IR R Program 1 Instruction 1 Instruction n data 1 data n M 13
1.3 Instruction Execution(2/9) Key point Program counter(PC)of CPU holds address of the in struction to be fetched next Fetched instruction is placed in the instruction register (Ir) Program counter(PC)of CPU is incremented after each fetch odel Opdatal Opcode Opdata2 data I data 2 R CPU
1.3 Instruction Execution (2/9) • Key point: • Program counter (PC) of CPU holds address of the instruction to be fetched next • Fetched instruction is placed in the instruction register (IR) • Program counter (PC) of CPU is incremented after each fetch 14
1.3 Instruction Execution(37 9) Instruction Cycle(指令周期) The processing required for a single instruction execution
1.3 Instruction Execution (3/9) • Instruction Cycle(指令周期) • The processing required for a single instruction execution 15