高级计算机体系结构设计及其在数据中心和云计算的应用Superscalar Decode for RiSC ISAsDecode Xinsns.per cycle (e.g,4-wide)-Justduplicatethehardware-Instructionsalignedat32-bitboundariesI-Fetch4-wide superscalarfetch32-bitinst32-bitinst32-bitinst32-bitinst32-bit instDecoderDecoderDecoderDecoderDecoderdecodeddecodeddecodeddecodeddecodedinstinstinstinstinstscalarsuperscalar
高级计算机体系结构设计及其在数据中心和云计算的应用 Superscalar Decode for RISC ISAs • Decode X insns. per cycle (e.g., 4-wide) – Just duplicate the hardware – Instructions aligned at 32-bit boundaries 1-Fetch 4-wide superscalar fetch 32-bit inst Decoder decoded inst scalar Decoder Decoder Decoder 32-bit inst Decoder decoded inst superscalar 4-wide superscalar fetch 32-bit inst 32-bit inst 32-bit inst decoded inst decoded inst decoded inst 1-Fetch
高级计算机体系结构设计及其在数据中心和云计算的应用CISC ISARisCfocus onfastaccess to information- Easy decode, IS, large RF's, Ds· Cisc focus on max expressiveness per min space-Designedinerawithfewertransistors,chips- Each memory access very expensive.Packasmuchworkintoasfewbytesaspossible.More“expressive"instructions-Better potential code generation in theory- More complex code generation in practice
高级计算机体系结构设计及其在数据中心和云计算的应用 CISC ISA • RISC focus on fast access to information – Easy decode, I$, large RF’s, D$ • CISC focus on max expressiveness per min space – Designed in era with fewer transistors, chips – Each memory access very expensive • Pack as much work into as few bytes as possible • More “expressive” instructions – Better potential code generation in theory – More complex code generation in practice
高级计算机体系结构设计及其在数据中心和云计算的应用ADDinRISCISAModeExampleMeaningRegisterADD R4,R3, R2R4=R3+R2
高级计算机体系结构设计及其在数据中心和云计算的应用 Mode Example Meaning Register ADD R4, R3, R2 R4 = R3 + R2 ADD in RISC ISA
高级计算机体系结构设计及其在数据中心和云计算的应用ADD in CISCISAModeExampleMeaningRegisterADD R4,R3R4 = R4 + R3ImmediateADD R4,#3R4 = R4 + 3DisplacementADD R4, 100(RI)R4 = R4 + Mem[100+RI]Register IndirectADD R4, (RI)R4 = R4 + Mem[RI]Indexed/BaseADD R3,(RI+R2)R3 = R3 + Mem[RI+R2]Direct/AbsoluteADD RI,(1234)RI = RI + Mem[1234]Memory IndirectADD RI, @(R3)RI = RI + Mem[Mem[R3]]Auto-lncrementADD RI,(R2)+RI = RI + Mem[R2]; R2++Auto-DecrementADD RI, -(R2)R2--; RI = RI + Mem[R2]
高级计算机体系结构设计及其在数据中心和云计算的应用 Mode Example Meaning Register ADD R4, R3 R4 = R4 + R3 Immediate ADD R4, #3 R4 = R4 + 3 Displacement ADD R4, 100(R1) R4 = R4 + Mem[100+R1] Register Indirect ADD R4, (R1) R4 = R4 + Mem[R1] ADD in CISC ISA Indexed/Base ADD R3, (R1+R2) R3 = R3 + Mem[R1+R2] Direct/Absolute ADD R1, (1234) R1 = R1 + Mem[1234] Memory Indirect ADD R1, @(R3) R1 = R1 + Mem[Mem[R3]] Auto-Increment ADD R1,(R2)+ R1 = R1 + Mem[R2]; R2++ Auto-Decrement ADD R1, -(R2) R2-; R1 = R1 + Mem[R2]
高级计算机体系结构设计及其在数据中心和云计算的应用x86CISC, stemmingfrom the original 4004 (~1971)Example:“"Move"instructions-GeneralPurposedatamovement: R>R,M>R, R>M,I>R,>MExchanges.EAX<>ECX,byteorderwithinaregister-StackManipulation.pushpopR<>Stack,PUSHA/POPA-TypeConversion-ConditionalMovesManywaysto dothesame/similaroperation
高级计算机体系结构设计及其在数据中心和云计算的应用 x86 • CISC, stemming from the original 4004 (~1971) • Example: “Move” instructions – General Purpose data movement • RR, MR, RM, IR, IM – Exchanges • EAX ↔ ECX, byte order within a register – Stack Manipulation • push pop R ↔ Stack, PUSHA/POPA – Type Conversion – Conditional Moves Many ways to do the same/similar operation