电子科技大学：《高等数字集成电路设计 Advanced Digital Integrated Circuits Design》课程教学资源（教学大纲，负责人：贺雅娟）

Digital Signal Processing • Signal & System • DSP system • Description for DSP FIR Filter Design & Implement • Digital Filter • Specification Design • Hardware Implementation Some Examples • Digital Down Converter • Central Processing Unit

Verilog for Verification • Testbench anatomy • Behavioral modeling for Testbench • Some examples Timing specification • Delay model • Timing verification • Pipeline technology Design For Test (DFT) Test vs. Verification Build In Self Test (BIST) Scan and Boundary Scan

• Synthesizable • Some experiences • Other syntax rules

FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller

• Topics Covered • Requirements • Others Info

• ASIC Classification • Design Flow and tools • Design Domains & Levels

• History, Present & Future • Manufacturing Process • Some Terms

广东海洋大学：《数字信号处理 Digital Signal Processing》课程教学资源（电子教案）

电子科技大学：《贝叶斯学习与随机矩阵及在无线通信中的应用 BI-RM-AWC》课程教学资源（学习资料）随机矩阵补充材料 Analysis of neural networks - a random matrix approach