ENC28J60PHLCON:PHYMODULELEDCONTROLREGISTERREGISTER2-2:R/W-0RW-0R/W-0RW-1R/W-1R/W-1RW-0R/W-0-LACFG3LACFG2LACFG1LACFGObit 15bit 8RW-0R/W-0RW-1RW-0R/W-0RW-0RW-1RW-xLBCFG3LBCFG2LBCFG1LBCFGOLFRQ1LFRQOSTRCHTbit 7bit oLegend:R=Readable bitW= Writable bitU=Unimplementedbit,readas'0''1' = Bit is set'0' = Bit is cleared-n = Value at PORx = Bit is unknownbit 15-14Reserved: Write as'o'bit 13-12Reserved:Write as‘1'bit 11-8LACFG3:LACFGO:LEDAConfiguration bits1111= Reserved1110 = Display duplex status and collision activity (always stretched)1101 = Display link status and transmit/receive activity (always stretched)1100 = Display link status and receive activity (always stretched)1011 = Blink slow1010=Blink fast1001=Off1000=On0111 =Display transmit and receive activity (stretchable)0110=Reserved0101 = Display duplex status0100=Display link status0011 =Display collision activity (stretchable)0010=Displayreceiveactivity (stretchable)0001=Display transmit activity (stretchable)0000=Reservedbit 7-4LBCFG3:LBCFGO:LEDB Configuration bits1110=Displayduplex status and collision activity (always stretched)1101=Display link status and transmit/receive activity (always stretched)1100=Display link status and receive activity (alwaysstretched)1011=Blink slow1010=Blink fast1001=Off1000=On0111 = Display transmit and receive activity (stretchable)0110=Reserved0101=Display duplex status0100=Display linkstatus0011=Displaycollisionactivity (stretchable)0010=Display receive activity (stretchable)0001 =Display transmit activity (stretchable)0000=Reservedbit 3-2LFRQ1:LFRQO:LEDPulseStretchTimeConfigurationbits (seeTable2-1)11=Reserved10=StretchLEDeventsbyTLSTRCH01=StretchLEDevents byTMSTRCH00=StretchLEDeventsbyTNSTRCHbit 1STRCH: LED Pulse Stretching Enable bit1 = Stretchable LEDevents willcause lengthened LED pulses basedon LFRQ1:LFRQOconfigurationStretchable LED events will onlybe displayed while they are occurring0=:bit oReserved: Write as'o'Preliminary2008 Microchip Technology Inc.DS39662C-page9
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 9 ENC28J60 REGISTER 2-2: PHLCON: PHY MODULE LED CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 r r r r LACFG3 LACFG2 LACFG1 LACFG0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-x LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ë0í -n = Value at POR ë1í = Bit is set ë0í = Bit is cleared x = Bit is unknown bit 15-14 Reserved: Write as ë0í bit 13-12 Reserved: Write as ë1í bit 11-8 LACFG3:LACFG0: LEDA Configuration bits 1111 = Reserved 1110 = Display duplex status and collision activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 1100 = Display link status and receive activity (always stretched) 1011 = Blink slow 1010 = Blink fast 1001 = Off 1000 = On 0111 = Display transmit and receive activity (stretchable) 0110 = Reserved 0101 = Display duplex status 0100 = Display link status 0011 = Display collision activity (stretchable) 0010 = Display receive activity (stretchable) 0001 = Display transmit activity (stretchable) 0000 = Reserved bit 7-4 LBCFG3:LBCFG0: LEDB Configuration bits 1110 = Display duplex status and collision activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 1100 = Display link status and receive activity (always stretched) 1011 = Blink slow 1010 = Blink fast 1001 = Off 1000 = On 0111 = Display transmit and receive activity (stretchable) 0110 = Reserved 0101 = Display duplex status 0100 = Display link status 0011 = Display collision activity (stretchable) 0010 = Display receive activity (stretchable) 0001 = Display transmit activity (stretchable) 0000 = Reserved bit 3-2 LFRQ1:LFRQ0: LED Pulse Stretch Time Configuration bits (see Table 2-1) 11 = Reserved 10 = Stretch LED events by TLSTRCH 01 = Stretch LED events by TMSTRCH 00 = Stretch LED events by TNSTRCH bit 1 STRCH: LED Pulse Stretching Enable bit 1 = Stretchable LED events will cause lengthened LED pulses based on LFRQ1:LFRQ0 configuration 0 = Stretchable LED events will only be displayed while they are occurring bit 0 Reserved: Write as ë0í
ENC28J60NOTES:PreliminaryDS39662C-page10 2008 Microchip Technology Inc
ENC28J60 DS39662C-page 10 Preliminary © 2008 Microchip Technology Inc. NOTES:
ENC28J603.0The Ethernet buffer contains transmit and receiveMEMORYORGANIZATIONmemoryusedbytheEthernet controllerina singleAll memoryintheENC28J60is implementedasstaticmemory space.Thesizes of the memory areas areRAM.Therearethreetypesof memory intheprogrammable by the host controllerusing the SPiENC28J60:interface.TheEthernetbuffermemorycanonlybeaccessedviathereadbuffermemoryandwritebuffer.Control RegistersmemorySPIcommands(seeSection4.2.2"Read:EthernetBufferBufferMemoryCommand"and Section4.2.4"Write?PHYRegistersBufferMemoryCommand").The Control registers'memory contains the registersThe PHY registers are used for configuration, controlthat are used for configuration, control and statusand status retrieval of the PHY module. The registersretrieval of the ENC28J60.The Control registers areare not directly accessiblethrough the SPl interface;directlyreadandwrittentobytheSPI interfacetheycanonlybeaccessedthroughMediaIndependentInterface Management (MIM) implemented in theMAC.Figure 3-1 shows the data memory organization for theENC28J60.FIGURE3-1:ENC28J60MEMORYORGANIZATIONECON1<1:0>Control RegistersEthernet Buffer00h0000hBuffer Pointers in Bank O= 00Bank 0?19h1AhCommon1FhRegisters00h= 01,Bank 119h1AhCommon1FhRegistersC00h=107Bank 219h1AhCommon1FFFhRegisters1Fh00h=11PHY RegistersBank 319h1Ah00hCommonRegisters1Fh1FhNote:Memoryareasarenotshowntoscale.ThesizeofthecontrolmemoryspacehasbeenscaledtoshowdetailPreliminaryDS39662C-page 11 2008 Microchip Technology Inc
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 11 ENC28J60 3.0 MEMORY ORGANIZATION All memory in the ENC28J60 is implemented as static RAM. There are three types of memory in the ENC28J60: ï Control Registers ï Ethernet Buffer ï PHY Registers The Control registersí memory contains the registers that are used for configuration, control and status retrieval of the ENC28J60. The Control registers are directly read and written to by the SPI interface. The Ethernet buffer contains transmit and receive memory used by the Ethernet controller in a single memory space. The sizes of the memory areas are programmable by the host controller using the SPI interface. The Ethernet buffer memory can only be accessed via the read buffer memory and write buffer memory SPI commands (see Section 4.2.2 ìRead Buffer Memory Commandî and Section 4.2.4 ìWrite Buffer Memory Commandî). The PHY registers are used for configuration, control and status retrieval of the PHY module. The registers are not directly accessible through the SPI interface; they can only be accessed through Media Independent Interface Management (MIIM) implemented in the MAC. Figure 3-1 shows the data memory organization for the ENC28J60. FIGURE 3-1: ENC28J60 MEMORY ORGANIZATION Common Registers Common Registers Common Registers Common Registers 00h 19h 1Ah 1Fh 00h 19h 1Ah 1Fh 00h 19h 1Ah 1Fh 00h 19h 1Ah 1Fh Bank 0 Bank 1 Bank 2 Bank 3 0000h 1FFFh = 00 = 01 = 10 = 11 ECON1<1:0> Control Registers Ethernet Buffer 00h 1Fh PHY Registers Note: Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail. Buffer Pointers in Bank 0
ENC28J603.1Some of theavailableaddresses are unimplementedControlRegistersAnyattemptstowritetotheselocationsareignoredThe Control registers provide the maininterfacewhile reads return 'o's.The register at address 1Ah inbetweenthehostcontrollerandtheon-chipEtherneteach bank is reserved;read and write operationscontroller logic.Writing to these registers controls theshould not be performed on this register. All otheroperation of the interface,while reading the registersreserved registersmaybe read,but their contents mustallows thehost controllertomonitor operations.notbe changed.When reading and writing to registerswhich contain reserved bits,any rules stated in theThe Control register memory is partitioned into fourregisterdefinitionshouldbeobserved.banks,selectablebythebankselectbits,BSEL1:BSELO,intheECON1register.Eachbank isControl registers for the ENC28J60 are generically32bytes longandaddressed bya5-bitaddress value.grouped as ETH, MAC and MIl registers. Registernames starting with "E" belong to the ETH group.Thelastfive locations (1Bh to1Fh)ofall bankspointtoaSimilarly,registers names starting with"MAbelong tocommon set of registers:EIE,EIR,ESTAT,ECON2 andthe MAC group and registers prefixed with"MI"belongECON1.Thesearekey registers used incontrollingandto the Mll group.monitoringtheoperation ofthedevice.Theircommonmapping allows easyaccess without switchingthebank.TheECON1andECON2registersarediscussed laterinthis section.ENC28J60CONTROLREGISTERMAPTABLE 3-1:Bank oBank1Bank2Bank3NameNameAddressAddressAddressNameAddressName00hERDPTL00hEHTO00hMACON100hMAADR501h01hEHT101h]ERDPTHReserved01hMAADR602h02hEHT202h02hEWRPTLMACON3MAADR303h03hEHT303h03hEWRPTHMACON4MAADR404h04h04hjETXSTLEHT4MABBIPG04hMAADR105h05hEHT505h05hETXSTHMAADR206h06hEHT606hMAIPGLETXNDL06hEBSTSD07hETXNDH07hEHT707hMAIPGH07hEBSTCON08hERXSTL08hEPMMO08hMACLCON108hEBSTCSL09h09h09h]09hERXSTHEPMM1MACLCON2EBSTCSHOAhERXNDLOAhEPMM2OAhMAMXFLLOAhMISTATOBhERXNDHOBhEPMM3OBhOBhMAMXFLH一ochoChoChERXRDPTLOChEPMM4Reserved-ODhERXRDPTHODhEPMM5ODhReservedODh一OEhOEhEPMM6OEhReservedOEhERXWRPTL一OFhOFhOFhOFhERXWRPTHEPMM7一-10hEDMASTL10hEPMCSL10h10hReserved一11h11h11h]11hEDMASTHEPMCSHReserved12h12h12hMICMD12hEREVIDEDMANDL一13hEDMANDH13h二13h13h114h14hEPMOL14h14hEDMADSTLMIREGADR一15h15hEPMOH15hReserved15hECOCONEDMADSTH16hEDMACSL16hReserved16h]MIWRL16hReserved17hEDMACSH17hReserved17hMIWRH17hEFLOCON18h18h18h18hERXFCONMIRDLEPAUSL19h19h19hMIRDH19hEPAUSHEPKTCNT一1Ah1Ah1Ah1AhReservedReservedReservedReserved1BhEIE1BhEIE1BhEIE1BhEIEEIREIREIREIR1Ch1Ch1Ch1Ch1DhESTAT1DhESTAT1DhESTAT1DhESTAT1EhECON21EhECON21EhECON21EhECON21Fh[ECON11FhECON11Fh|ECON11FhECON1PreliminaryDS39662C-page 12 2008 Microchip Technology Inc
ENC28J60 DS39662C-page 12 Preliminary © 2008 Microchip Technology Inc. 3.1 Control Registers The Control registers provide the main interface between the host controller and the on-chip Ethernet controller logic. Writing to these registers controls the operation of the interface, while reading the registers allows the host controller to monitor operations. The Control register memory is partitioned into four banks, selectable by the bank select bits, BSEL1:BSEL0, in the ECON1 register. Each bank is 32 bytes long and addressed by a 5-bit address value. The last five locations (1Bh to 1Fh) of all banks point to a common set of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used in controlling and monitoring the operation of the device. Their common mapping allows easy access without switching the bank. The ECON1 and ECON2 registers are discussed later in this section. Some of the available addresses are unimplemented. Any attempts to write to these locations are ignored while reads return ë0ís. The register at address 1Ah in each bank is reserved; read and write operations should not be performed on this register. All other reserved registers may be read, but their contents must not be changed. When reading and writing to registers which contain reserved bits, any rules stated in the register definition should be observed. Control registers for the ENC28J60 are generically grouped as ETH, MAC and MII registers. Register names starting with ìEî belong to the ETH group. Similarly, registers names starting with ìMAî belong to the MAC group and registers prefixed with ìMIî belong to the MII group. TABLE 3-1: ENC28J60 CONTROL REGISTER MAP Bank 0 Bank 1 Bank 2 Bank 3 Address Name Address Name Address Name Address Name 00h ERDPTL 00h EHT0 00h MACON1 00h MAADR5 01h ERDPTH 01h EHT1 01h Reserved 01h MAADR6 02h EWRPTL 02h EHT2 02h MACON3 02h MAADR3 03h EWRPTH 03h EHT3 03h MACON4 03h MAADR4 04h ETXSTL 04h EHT4 04h MABBIPG 04h MAADR1 05h ETXSTH 05h EHT5 05h ó 05h MAADR2 06h ETXNDL 06h EHT6 06h MAIPGL 06h EBSTSD 07h ETXNDH 07h EHT7 07h MAIPGH 07h EBSTCON 08h ERXSTL 08h EPMM0 08h MACLCON1 08h EBSTCSL 09h ERXSTH 09h EPMM1 09h MACLCON2 09h EBSTCSH 0Ah ERXNDL 0Ah EPMM2 0Ah MAMXFLL 0Ah MISTAT 0Bh ERXNDH 0Bh EPMM3 0Bh MAMXFLH 0Bh ó 0Ch ERXRDPTL 0Ch EPMM4 0Ch Reserved 0Ch ó 0Dh ERXRDPTH 0Dh EPMM5 0Dh Reserved 0Dh ó 0Eh ERXWRPTL 0Eh EPMM6 0Eh Reserved 0Eh ó 0Fh ERXWRPTH 0Fh EPMM7 0Fh ó 0Fh ó 10h EDMASTL 10h EPMCSL 10h Reserved 10h ó 11h EDMASTH 11h EPMCSH 11h Reserved 11h ó 12h EDMANDL 12h ó 12h MICMD 12h EREVID 13h EDMANDH 13h ó 13h ó 13h ó 14h EDMADSTL 14h EPMOL 14h MIREGADR 14h ó 15h EDMADSTH 15h EPMOH 15h Reserved 15h ECOCON 16h EDMACSL 16h Reserved 16h MIWRL 16h Reserved 17h EDMACSH 17h Reserved 17h MIWRH 17h EFLOCON 18h ó 18h ERXFCON 18h MIRDL 18h EPAUSL 19h ó 19h EPKTCNT 19h MIRDH 19h EPAUSH 1Ah Reserved 1Ah Reserved 1Ah Reserved 1Ah Reserved 1Bh EIE 1Bh EIE 1Bh EIE 1Bh EIE 1Ch EIR 1Ch EIR 1Ch EIR 1Ch EIR 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT 1Dh ESTAT 1Eh ECON2 1Eh ECON2 1Eh ECON2 1Eh ECON2 1Fh ECON1 1Fh ECON1 1Fh ECON1 1Fh ECON1
ENC28J60TABLE 3-2:ENC28J60CONTROLREGISTERSUMMARYDetailsValueBit 7Register NameBit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit oononResetPageEIELINKIETXIE65INTIEPKTIEDMAIETXERIERXERIE0000 0000EIRPKTIFDMAIFLINKIFTXIF:TXERIFRXERIF66--000 0000CLKRDY(1)64 ESTATINTBUFERrLATECOL-RXBUSYTXABRT0000-000ECON2AUTOINCPKTDECPWRSVLVRPS-一一1000 0---16ECON1RXRSTDMASTTXRTSRXENBSEL1BSELO15TXRSTCSUMEN0000000017ERDPTLRead Pointer Low Byte ERDPT<7:0>)11111010ERDPTH--一Read Pointer High Byte (ERDPT<12:8>)---0 01011717EWRPTLWite Pointer Low Byte (EWRPT<7:0>)00000000EWRPTH一一17-Write Pointer High Byte (EWRPT<12:8>)---0 0000ETXSTLTX Start Low Byte (ETXST<7:0>)0000000017ETXSTHTX Start High Byte (ETXST<12:8>)17-----0 0000-17ETXNDLTX End Low Byte (ETXND<7:0>)0000000017ETXNDH1-1TX End High Byte (ETXND<12:8>)---0 0000ERXSTLRX Start Low Byte (ERXST<7:0>)1111171010ERXSTH17RX Start High Byte (ERXST<12:8>)---00101-ERXNDLRX End Low Byte (ERXND<7:0>)171111 111117ERXNDH--RX End High Byte (ERXND<12:8>)---1 1111-1111101017ERXRDPTLRX RD Pointer Low Byte (ERXRDPT<7:0>)17ERXRDPTH一--RX RD Pointer High Byte (ERXRDPT<12:8>)---0 0101ERXWRPTL17RX WR Pointer Low Byte (ERXWRPT<7:0>)00000000ERXWRPTH一一一RXWRPointerHighByte (ERXWRPT<12:8>)---0 000017EDMASTL0000000071DMA Start Low Byte (EDMAST<7:0>)71EDMASTH1DMA Start High Byte (EDMAST<12:8>)---0 000071EDMANDLDMA End Low Byte (EDMAND<7:0>)00000000EDMANDHDMA End High Byte (EDMAND<12:8>)71一----00000-EDMADSTLDMA Destination Low Byte (EDMADST<7:0>)0000710000EDMADSTHDMA Destination High Byte (EDMADST<12:8>)--0 000071一-一72EDMACSLDMA Checksum Low Byte (EDMACS<7:0>)00000000EDMACSH0000000072DMA Checksum High Byte (EDMACS<15:8>)EHTOHash Table Byte 0 (EHT<7:0>)0000000052EHT10000000052Hash Table Byte 1 (EHT<15:8>)EHT252Hash Table Byte 2 (EHT<23:16>)00000000EHT3Hash Table Byte 3 (EHT<31:24>)0000000052EHT45200000000Hash Table Byte 4 (EHT<39:32>)EHT552Hash Table Byte 5 (EHT<47:40>)00000000EHT60000000052[Hash Table Byte 6 (EHT<55:48>)EHT7000052Hash Table Byte 7 (EHT<63:56>)0000EPMMOPattem Match Mask Byte 0 (EPMM<7:0>)0000000051EPMM151Pattern Match Mask Byte 1 (EPMM<15:8>)00000000EPMM20000000051Pattern Match Mask Byte 2 (EPMM<23:16>)EPMM351Pattem Match Mask Byte 3 (EPMM<31:24>)00000000EPMM40000000051Pattern Match Mask Byte 4 (EPMM<39:32>)EPMM551Pattern Match Mask Byte 5 (EPMM<47:40>)00000000EPMM6Pattern Match Mask Byte 6 (EPMM<55:48>)0000000051EPMM70000000051Pattern Match Mask Byte 7 (EPMM<63:56>)Legend:x = unknown, u = unchanged, -= unimplemented, g = value depends on condition, r = reserved, do not modify.NNoteCLKRDY resets to 'o'on Power-on Reset but is unaffected on all other Resets.2: EREVID is a read-only register.3:ECOCON resets to ---- -1oo' on Power-on Reset and '-----uuu' on all other Resets.PreliminaryDS39662C-page 13 2008 Microchip Technology Inc
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 13 ENC28J60 TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Reset Details on Page EIE INTIE PKTIE DMAIE LINKIE TXIE r TXERIE RXERIE 0000 0000 65 EIR ó PKTIF DMAIF LINKIF TXIF r TXERIF RXERIF -000 0000 66 ESTAT INT BUFER r LATECOL ó RXBUSY TXABRT CLKRDY(1) 0000 -000 64 ECON2 AUTOINC PKTDEC PWRSV r VRPS ó ó ó 1000 0- 16 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 0000 0000 15 ERDPTL Read Pointer Low Byte ERDPT<7:0>) 1111 1010 17 ERDPTH ó ó ó Read Pointer High Byte (ERDPT<12:8>) -0 0101 17 EWRPTL Write Pointer Low Byte (EWRPT<7:0>) 0000 0000 17 EWRPTH ó ó ó Write Pointer High Byte (EWRPT<12:8>) -0 0000 17 ETXSTL TX Start Low Byte (ETXST<7:0>) 0000 0000 17 ETXSTH ó ó ó TX Start High Byte (ETXST<12:8>) -0 0000 17 ETXNDL TX End Low Byte (ETXND<7:0>) 0000 0000 17 ETXNDH ó ó ó TX End High Byte (ETXND<12:8>) -0 0000 17 ERXSTL RX Start Low Byte (ERXST<7:0>) 1111 1010 17 ERXSTH ó ó ó RX Start High Byte (ERXST<12:8>) -0 0101 17 ERXNDL RX End Low Byte (ERXND<7:0>) 1111 1111 17 ERXNDH ó ó ó RX End High Byte (ERXND<12:8>) -1 1111 17 ERXRDPTL RX RD Pointer Low Byte (ERXRDPT<7:0>) 1111 1010 17 ERXRDPTH ó ó ó RX RD Pointer High Byte (ERXRDPT<12:8>) -0 0101 17 ERXWRPTL RX WR Pointer Low Byte (ERXWRPT<7:0>) 0000 0000 17 ERXWRPTH ó ó ó RX WR Pointer High Byte (ERXWRPT<12:8>) -0 0000 17 EDMASTL DMA Start Low Byte (EDMAST<7:0>) 0000 0000 71 EDMASTH ó ó ó DMA Start High Byte (EDMAST<12:8>) -0 0000 71 EDMANDL DMA End Low Byte (EDMAND<7:0>) 0000 0000 71 EDMANDH ó ó ó DMA End High Byte (EDMAND<12:8>) -0 0000 71 EDMADSTL DMA Destination Low Byte (EDMADST<7:0>) 0000 0000 71 EDMADSTH ó ó ó DMA Destination High Byte (EDMADST<12:8>) -0 0000 71 EDMACSL DMA Checksum Low Byte (EDMACS<7:0>) 0000 0000 72 EDMACSH DMA Checksum High Byte (EDMACS<15:8>) 0000 0000 72 EHT0 Hash Table Byte 0 (EHT<7:0>) 0000 0000 52 EHT1 Hash Table Byte 1 (EHT<15:8>) 0000 0000 52 EHT2 Hash Table Byte 2 (EHT<23:16>) 0000 0000 52 EHT3 Hash Table Byte 3 (EHT<31:24>) 0000 0000 52 EHT4 Hash Table Byte 4 (EHT<39:32>) 0000 0000 52 EHT5 Hash Table Byte 5 (EHT<47:40>) 0000 0000 52 EHT6 Hash Table Byte 6 (EHT<55:48>) 0000 0000 52 EHT7 Hash Table Byte 7 (EHT<63:56>) 0000 0000 52 EPMM0 Pattern Match Mask Byte 0 (EPMM<7:0>) 0000 0000 51 EPMM1 Pattern Match Mask Byte 1 (EPMM<15:8>) 0000 0000 51 EPMM2 Pattern Match Mask Byte 2 (EPMM<23:16>) 0000 0000 51 EPMM3 Pattern Match Mask Byte 3 (EPMM<31:24>) 0000 0000 51 EPMM4 Pattern Match Mask Byte 4 (EPMM<39:32>) 0000 0000 51 EPMM5 Pattern Match Mask Byte 5 (EPMM<47:40>) 0000 0000 51 EPMM6 Pattern Match Mask Byte 6 (EPMM<55:48>) 0000 0000 51 EPMM7 Pattern Match Mask Byte 7 (EPMM<63:56>) 0000 0000 51 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify. Note 1: CLKRDY resets to ë0í on Power-on Reset but is unaffected on all other Resets. 2: EREVID is a read-only register. 3: ECOCON resets to ë- -100í on Power-on Reset and ë- -uuuí on all other Resets