《嵌入式应用开发》课程教学资源（文献资料）ENC28J60 Data Sheet Stand-Alone Ethernet Controller with SPI Interface.pdf_P6-P10

ENC28J60 DS39662C-page 4 Preliminary © 2008 Microchip Technology Inc. FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description SPDIP, SOIC, SSOP QFN VCAP 1 25 P ó 2.5V output from internal regulator. A low Equivalent Series Resistance (ESR) capacitor, with a typical value of 10 mF and a minimum value of 1 mF to ground, must be placed on this pin. VSS 2 26 P ó Ground reference. CLKOUT 3 27 O ó Programmable clock output pin.(1) INT 4 28 O ó INT interrupt output pin.(2) NC 5 1 O ó Reserved function; always leave unconnected. SO 6 2 O ó Data out pin for SPI interface.(2) SI 7 3 I ST Data in pin for SPI interface.(3) SCK 8 4 I ST Clock in pin for SPI interface.(3) CS 9 5 I ST Chip select input pin for SPI interface.(3,4) RESET 10 6 I ST Active-low device Reset input.(3,4) VSSRX 11 7 P ó Ground reference for PHY RX. TPIN- 12 8 I ANA Differential signal input. TPIN+ 13 9 I ANA Differential signal input. RBIAS 14 10 I ANA Bias current pin for PHY. Must be tied to ground via a resistor (refer to Section 2.4 ìMagnetics, Termination and Other External Componentsî for details). VDDTX 15 11 P ó Positive supply for PHY TX. TPOUT- 16 12 O ó Differential signal output. TPOUT+ 17 13 O ó Differential signal output. VSSTX 18 14 P ó Ground reference for PHY TX. VDDRX 19 15 P ó Positive 3.3V supply for PHY RX. VDDPLL 20 16 P ó Positive 3.3V supply for PHY PLL. VSSPLL 21 17 P ó Ground reference for PHY PLL. VSSOSC 22 18 P ó Ground reference for oscillator. OSC1 23 19 I ANA Oscillator input. OSC2 24 20 O ó Oscillator output. VDDOSC 25 21 P ó Positive 3.3V supply for oscillator. LEDB 26 22 O ó LEDB driver pin.(5) LEDA 27 23 O ó LEDA driver pin.(5) VDD 28 24 P ó Positive 3.3V supply. Legend: I = Input, O = Output, P = Power, ANA = Analog Signal Input, ST = Schmitt Trigger Note 1: Pins have a maximum current capacity of 8 mA. 2: Pins have a maximum current capacity of 4 mA. 3: Pins are 5V tolerant. 4: Pins have an internal weak pull-up to VDD. 5: Pins have a maximum current capacity of 12 mA. TRANSFORMER MCU TX/RX Buffer MAC PHY LEDA LEDB SI SO SCK INT SDO SDI SCK INTX ENC28J60 TPIN+/- TPOUT+/- ETHERNET RJ45 I/O CS

© 2008 Microchip Technology Inc. Preliminary DS39662C-page 5 ENC28J60 2.0 EXTERNAL CONNECTIONS 2.1 Oscillator The ENC28J60 is designed to operate at 25 MHz with a crystal connected to the OSC1 and OSC2 pins. The ENC28J60 design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer specifications. A typical oscillator circuit is shown in Figure 2-1. The ENC28J60 may also be driven by an external clock source connected to the OSC1 pin as shown in Figure 2-2. FIGURE 2-1: CRYSTAL OSCILLATOR OPERATION FIGURE 2-2: EXTERNAL CLOCK SOURCE(1) 2.2 Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire until 7500 OSC1 clock cycles (300 μs) pass after Power-on Reset or wake-up from Power-Down mode occurs. During the delay, all Ethernet registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set ECON1.TXRTS), enable reception of packets (set ECON1.RXEN) or access any MAC, MII or PHY registers during this period. When the OST expires, the CLKRDY bit in the ESTAT register will be set. The application software should poll this bit as necessary to determine when normal device operation can begin. C1 C2 XTAL OSC2 RS(1) OSC1 RF(2) To Internal Logic Note 1: A series resistor, RS, may be required for AT strip cut crystals. 2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ. ENC28J60 3.3V Clock from External System OSC1 Open OSC2 (2) Note 1: Duty cycle restrictions must be observed. 2: A resistor to ground may be used to reduce system noise. This may increase system current. ENC28J60 Note: After a Power-on Reset, or the ENC28J60 is removed from Power-Down mode, the CLKRDY bit must be polled before transmitting packets, enabling packet reception or accessing any MAC, MII or PHY registers

ENC28J602.3CLKOUTPinAdditionally,Power-Downmodemaybevalue).entered and the CLKOUT function will continuetoTheclock out pin isprovidedto the systemdesignerforoperate.When Power-Down mode is cancelled, theuseas thehostcontrollerclockorasaclocksourceforOST will bereset buttheCLKOUT function willotherdevicesin the system.TheCLKOUThasancontinue.When theCLKOUT function is disabledintemalprescalerwhichcandividetheoutputby1,2,(ECOCON=o),theCLKOUTpinisdrivenlow3,4or8.TheCLKOUTfunctionisenabledand theThe CLKOUT function is designed to ensure that mini-prescaler isselectedviatheECOCONregistermum timings are preserved when the CLKOUT pin(Register 2-1).function is enabled, disabled or the prescaler value isTocreateaclean clock signal,theCLKOUTpin isheldchanged.No high or low pulses will be outputted whichlowforaperiod whenpower is firstapplied.Aftertheexceed the frequency specified by the ECOCONPower-on Reset ends, the OST will begin counting.configuration.However,whenswitchingfrequencies,aWhen the OST expires, the CLKOUT pin willbegin out-delaybetweentwoandeightOSC1clockperiods willputting its default frequency of 6.25 MHz (main clockoccurwhere no clock pulses will be produced (seedivided by 4).At anyfuture time thatthe ENC28J60 isFigure 2-3). During this period, CLKOUT will be heldreset by softwareor the RESETpin, the CLKOUT func-low.tion will not be altered (ECOCONwill not changeFIGURE 2-3:CLKOUTTRANSITION1ECOCON80nsto320nsDelayChangedECOCON:CLOCKOUTPUTCONTROLREGISTERREGISTER 2-1:U-0U-0U-0U-0U-OR/W-1R/W-0R/W-0COCON2COCON1COCONObit 7bit oLegend:R= Readable bitW= Writable bitU=Unimplementedbit,readas01'= Bit is set-n = Value at POR'0'=Bit is clearedx = Bit is unknownbit 7-3Unimplemented:Readas'o'bit 2-0CocoN2:cocoNo:ClockOutputConfigurationbits11x=Reservedforfactorytest.Donotuse.Glitchpreventionnotassured.101=CLKOUT outputsmain clock divided by8 (3.125MHz)100=CLKOUToutputsmainclockdividedby4(6.25MHz)011=CLKOUToutputsmainclockdividedby3(8.333333MHz)010=CLKOUT outputsmain clock divided by2 (12.5MHz)001=CLKOUToutputsmainclockdividedby1(25MHz)000=CLKOUT isdisabled.Thepin is driven low.PreliminaryDS39662C-page 62008 Microchip Technology Inc

ENC28J60 DS39662C-page 6 Preliminary © 2008 Microchip Technology Inc. 2.3 CLKOUT Pin The clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register (Register 2-1). To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting. When the OST expires, the CLKOUT pin will begin outputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT function will not be altered (ECOCON will not change value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low. The CLKOUT function is designed to ensure that minimum timings are preserved when the CLKOUT pin function is enabled, disabled or the prescaler value is changed. No high or low pulses will be outputted which exceed the frequency specified by the ECOCON configuration. However, when switching frequencies, a delay between two and eight OSC1 clock periods will occur where no clock pulses will be produced (see Figure 2-3). During this period, CLKOUT will be held low. FIGURE 2-3: CLKOUT TRANSITION ECOCON Changed 80 ns to 320 ns Delay REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 ó ó ó ó ó COCON2 COCON1 COCON0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ë0í -n = Value at POR ë1í = Bit is set ë0í = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ë0í bit 2-0 COCON2:COCON0: Clock Output Configuration bits 11x = Reserved for factory test. Do not use. Glitch prevention not assured. 101 = CLKOUT outputs main clock divided by 8 (3.125 MHz) 100 = CLKOUT outputs main clock divided by 4 (6.25 MHz) 011 = CLKOUT outputs main clock divided by 3 (8.333333 MHz) 010 = CLKOUT outputs main clock divided by 2 (12.5 MHz) 001 = CLKOUT outputs main clock divided by 1 (25 MHz) 000 = CLKOUT is disabled. The pin is driven low

ENC28J602.4Acommon-modechokeontheTPOUTinterface,placedMagnetics,TerminationandOtherbetweentheTPOUTpinsandtheEthernettransformerExternalComponents(not shown), is not recommended. If a common-modeTocomplete the Ethernet interface,the ENC28J60choke is usedto reduce EMI emissions,it should berequiresseveralstandardcomponentstobeinstalledplacedbetweentheEthernettransformerandpins1andexternally.Thesecomponents shouldbeconnectedas2of theRJ-45connector.Many Ethernettransformershown in Figure 2-4.modules includecommon-modechokes insidethesamedevicepackage.ThetransformersshouldhaveatleastThe internal analog circuitry in the PHY module requiresthe isolation rating specified in Table 16-5 to protectthatanexternal2.32k2,1%resistorbeattachedfromagainst static voltagesandmeetIEEE802.3isolationRBIAS to ground. The resistor influences the TPOUT+/-requirements(seeSection16.0"ElectricalCharacter-signal amplitude.Theresistorshould beplacedas closeistics"for specific transformer requirements).Bothaspossibletothechipwithnoimmediatelyadjacenttransmit and receive interfaces additionally require twosignaltracestopreventnoisecapacitivelycoupling intoresistors and a capacitor to properly terminate thethepin and affectingthe transmit behavior.Itistransmission line, minimizing signal reflections.recommended that theresistor bea surface mounttypeAllpowersupplypinsmustbeexternallyconnectedtoSome of the device's digital logicoperates at a nominathe same power source.Similarly,all ground refer-2.5V.An on-chip voltage regulator is incorporated toences must beexternallyconnectedto the samegeneratethis voltage.The only external componentground node.EachVDD andVsspinpair shouldhaverequiredisanexternalfiltercapacitor,connectedfroma0.1μFceramicbypasscapacitor(not shown in theVcAptoground.Thecapacitormusthavelowequiva-schematic)placedasclosetothepinsaspossible.lent series resistance (ESR), with a typical value of10μF,and a minimum value of 1μF.The internalSince relatively high currents are necessary to operateregulatoris notdesignedtodriveexternal loads.the twisted-pair interface, all wires should be kept asshort aspossible.Reasonablewirewidths shouldbeOn the TPIN+/TPIN-and TPOUT+/TPOUT-pinsused on power wires to reduce resistive loss. If the1:1centertapedpulsetransformers,ratedforEthernetdifferential data lines cannot be kept short, they shouldoperations,are required.When theEthernetmodule isberouted insuchawayastohavea1002characteristicenabled, current is continually sunk through bothimpedance.TPOUTpins.WhenthePHYis activelytransmitting,adifferential voltage is created on the Ethernet cable byvaryingtherelativecurrentsunkbyTPOUT+comparedto TPOUT-.FIGURE 2-4:ENC28J60ETHERNETTERMINATIONANDEXTERNALCONNECTIONS3.3VRJ-45ENC28J60MCULTPOUT+FerritecsVO-Bead(1,3)SCKSCK2?SISDO0.1 μF(3)≥49.90,1%SOSDI-13TPOUT-1:1CT-TPIN+4Level49.92, 1%Shift&I Logic(2) ;4531149.92,1%0.1 μFINT-INTO61:1 CTTPIN-RBIAS7VCAPLEDALEDBMMZ87503|7502(3）7502(3|750(3≥ 2.32 k2, 1%10 μFX1 nF, 2 kV(3)IN1:NoteFerrite Bead should be rated for at least 80 mARequired only if the microcontrolleris operating at 5V. See Section 2.5 "VO Levels" for more information.2:3:These components are installed for EMI reduction purposes.Preliminary2008 Microchip Technology inc.DS39662C-page 7

© 2008 Microchip Technology Inc. Preliminary DS39662C-page 7 ENC28J60 2.4 Magnetics, Termination and Other External Components To complete the Ethernet interface, the ENC28J60 requires several standard components to be installed externally. These components should be connected as shown in Figure 2-4. The internal analog circuitry in the PHY module requires that an external 2.32 kΩ, 1% resistor be attached from RBIAS to ground. The resistor influences the TPOUT+/- signal amplitude. The resistor should be placed as close as possible to the chip with no immediately adjacent signal traces to prevent noise capacitively coupling into the pin and affecting the transmit behavior. It is recommended that the resistor be a surface mount type. Some of the deviceís digital logic operates at a nominal 2.5V. An on-chip voltage regulator is incorporated to generate this voltage. The only external component required is an external filter capacitor, connected from VCAP to ground. The capacitor must have low equivalent series resistance (ESR), with a typical value of 10 μF, and a minimum value of 1 μF. The internal regulator is not designed to drive external loads. On the TPIN+/TPIN- and TPOUT+/TPOUT- pins, 1:1 center taped pulse transformers, rated for Ethernet operations, are required. When the Ethernet module is enabled, current is continually sunk through both TPOUT pins. When the PHY is actively transmitting, a differential voltage is created on the Ethernet cable by varying the relative current sunk by TPOUT+ compared to TPOUT-. A common-mode choke on the TPOUT interface, placed between the TPOUT pins and the Ethernet transformer (not shown), is not recommended. If a common-mode choke is used to reduce EMI emissions, it should be placed between the Ethernet transformer and pins 1 and 2 of the RJ-45 connector. Many Ethernet transformer modules include common-mode chokes inside the same device package. The transformers should have at least the isolation rating specified in Table 16-5 to protect against static voltages and meet IEEE 802.3 isolation requirements (see Section 16.0 ìElectrical Characteristicsî for specific transformer requirements). Both transmit and receive interfaces additionally require two resistors and a capacitor to properly terminate the transmission line, minimizing signal reflections. All power supply pins must be externally connected to the same power source. Similarly, all ground references must be externally connected to the same ground node. Each VDD and VSS pin pair should have a 0.1 μF ceramic bypass capacitor (not shown in the schematic) placed as close to the pins as possible. Since relatively high currents are necessary to operate the twisted-pair interface, all wires should be kept as short as possible. Reasonable wire widths should be used on power wires to reduce resistive loss. If the differential data lines cannot be kept short, they should be routed in such a way as to have a 100Ω characteristic impedance. FIGURE 2-4: ENC28J60 ETHERNET TERMINATION AND EXTERNAL CONNECTIONS I/O SCK SDO SDI INT0 MCU Level Shift Logic(2) CS SCK SI SO INT ENC28J60 VCAP LEDA LEDB RBIAS TPOUT+ TPOUTTPIN+ TPIN- 10 μF Note 1: Ferrite Bead should be rated for at least 80 mA. 2: Required only if the microcontroller is operating at 5V. See Section 2.5 ìI/O Levelsî for more information. 3: These components are installed for EMI reduction purposes. Ferrite Bead(1,3) 3.3V 2.32 kΩ, 1% 1 2 3 4 5 6 7 8 RJ-45 1:1 CT 1:1 CT 1 nF, 2 kV(3) 75Ω(3) 75Ω(3) 75Ω(3) 75Ω(3) 49.9Ω, 1% 49.9Ω, 1% 49.9Ω, 1% 49.9Ω, 1% 0.1 μF(3) 0.1 μF 1

ENC28J602.5/OLevels2.6LED ConfigurationTheENC28J60isa3.3Vpart:howeveritwasTheLEDAand LEDB pins support automatic polaritydesignedtobeeasilyintegratedinto5Vsystems.Thedetection on Reset.TheLEDscan be connected suchSPI CS, SCK and SI inputs, as well as the RESET pin,that the pinmust source current to tun the LED on,orare all 5V tolerant. On the other hand, if the hostalternately connected such that the pin must sink cur-controlleris operated at5V,it quite likelywill not berentto turn the LED on. Upon system Reset, thewithin specifications when its SPI and interrupt inputsENC28J60willdetecthowtheLED isconnectedandare driven bythe 3.3VCMOS outputs onthebegin drivingthe LEDtothedefault stateconfiguredbyENC28J60.Aunidirectional leveltranslatorwouldbethePHLCON register.If the LED polarity is changedwhile the ENC28J60 is operating,the new polarity willnecessary.notbe detected until the next system Reset occurs.Aneconomical74HCT08(quadANDgate),74ACT125(quad 3-state buffer) or many other 5V CMOS chipsLEDB is unique in that the connection of the LED iswithTTLlevelinputbuffersmaybeusedtoprovidetheautomaticallyread onResetanddetermineshowtainitialize thePHCON1.PDPXMD bit.If the pin sourcesnecessary level shifting.The use of 3-state bufferspermits easyintegration intosystemswhich sharethecurrent to illuminate the LED,the bit is cleared onSPI bus with other devices. Figure 2-5 and Figure 2-6ResetandthePHYdefaultstohalf-duplexoperation.Ifshowexampletranslationschemes.the pin sinks currentto illuminate the LED, the bit is setonResetandthePHYdefaultstofull-duplexoperationFIGURE 2-5:LEVELSHIFTINGUSINGFigure2-7showsthetwoavailableoptions.If noLEDisattachedtotheLEDBpin,thePDPXMDbit will resetANDGATESto an indeterminate value.MCUENC28J60FIGURE 2-7:LEDBPOLARITYANDRESETCONFIGURATIONcs+VOOPTIONSVSCKSCKSISO+Full-Duplex Operation:Q+3.3VPDPXMD =1sIsoVCLKOUTOSC1LEDBINTINTO斤Half-Duplex Operation:PDPXMD=0FIGURE2-6:LEVELSHIFTINGUSINGLEDB13-STATEBUFFERSMCUENC28J60csVO-SCKSCKSIsOTheLEDscan alsobeconfigured separatelyto controltheiroperating polarity (on oroff when active),blinkrateSOSIand blink stretch interval.The options are controlled bytheLACFG3:LACFGO andLBCFG3:LBCFG0bitsCLKOUTOSC1TypicalvaluesforblinkstretcharelistedinTable2-1.INTINTOTABLE 2-1:LEDBLINKSTRETCHLENGTHStretch LengthTypical Stretch (ms)40TNSTRCH (normal)70TMSTRCH (medium)140TLSTRCH (long)PreliminaryDS39662C-page 8?2008MicrochipTechnology Inc

ENC28J60 DS39662C-page 8 Preliminary © 2008 Microchip Technology Inc. 2.5 I/O Levels The ENC28J60 is a 3.3V part; however, it was designed to be easily integrated into 5V systems. The SPI CS, SCK and SI inputs, as well as the RESET pin, are all 5V tolerant. On the other hand, if the host controller is operated at 5V, it quite likely will not be within specifications when its SPI and interrupt inputs are driven by the 3.3V CMOS outputs on the ENC28J60. A unidirectional level translator would be necessary. An economical 74HCT08 (quad AND gate), 74ACT125 (quad 3-state buffer) or many other 5V CMOS chips with TTL level input buffers may be used to provide the necessary level shifting. The use of 3-state buffers permits easy integration into systems which share the SPI bus with other devices. Figure 2-5 and Figure 2-6 show example translation schemes. FIGURE 2-5: LEVEL SHIFTING USING AND GATES FIGURE 2-6: LEVEL SHIFTING USING 3-STATE BUFFERS 2.6 LED Configuration The LEDA and LEDB pins support automatic polarity detection on Reset. The LEDs can be connected such that the pin must source current to turn the LED on, or alternately connected such that the pin must sink current to turn the LED on. Upon system Reset, the ENC28J60 will detect how the LED is connected and begin driving the LED to the default state configured by the PHLCON register. If the LED polarity is changed while the ENC28J60 is operating, the new polarity will not be detected until the next system Reset occurs. LEDB is unique in that the connection of the LED is automatically read on Reset and determines how to initialize the PHCON1.PDPXMD bit. If the pin sources current to illuminate the LED, the bit is cleared on Reset and the PHY defaults to half-duplex operation. If the pin sinks current to illuminate the LED, the bit is set on Reset and the PHY defaults to full-duplex operation. Figure 2-7 shows the two available options. If no LED is attached to the LEDB pin, the PDPXMD bit will reset to an indeterminate value. FIGURE 2-7: LEDB POLARITY AND RESET CONFIGURATION OPTIONS The LEDs can also be configured separately to control their operating polarity (on or off when active), blink rate and blink stretch interval. The options are controlled by the LACFG3:LACFG0 and LBCFG3:LBCFG0 bits. Typical values for blink stretch are listed in Table 2-1. TABLE 2-1: LED BLINK STRETCH LENGTH I/O SCK SO SI INT0 MCU CS SCK SI SO INT ENC28J60 OSC1 CLKOUT I/O SCK SO SI INT0 MCU CS SCK SI SO INT ENC28J60 OSC1 CLKOUT Stretch Length Typical Stretch (ms) TNSTRCH (normal) 40 TMSTRCH (medium) 70 TLSTRCH (long) 140 LEDB Full-Duplex Operation: +3.3V PDPXMD = 1 LEDB Half-Duplex Operation: PDPXMD = 0