ENC28J60TABLE 3-2:ENC28J60CONTROLREGISTERSUMMARY(CONTINUED)DetailsValueBit 2Register NameBit 7Bit6Bit 5Bit 4Bit 3Bit 1Bit oononResetPageEPMCSL51Pattern Match Checksum Low Byte (EPMCS<7:0>)00000000EPMCSH51Pattern Match Checksum High Byte (EPMCS<15:0>)0000000051EPMOLPattern Match Offset Low Byte (EPMO<7:0>)00000000EPMOH51一一一Pattern Match Ofset High Byte (EPMO<12:8>)---00000ERXFCONUCENCRCENPMENMPENHTENMCENBCEN48 ANDOR1010000143EPKTCNTEthernet Packet Count00000000MACON1一-TXPAUSRXPAUSPASSALLMARXEN34 二r---0 000035MACON3PADCFG2PADCFG1PADCFGOTXCRCENPHDRENHFRMENFRMLNENFULDPX00000000MACON4-DEFERBPENNOBKOFFI--000-0036一MABBIPG一-000 000036Back-to-Back Inter-Packet Gap (BBIPG<6:0>)MAIPGL34-Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)-000000034 MAIPGH--000 0000Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)34MACLCON1一一一一RetransmissionMaximum (RETMAX<3:0>)1111---34MACLCON2Collision Window (COLWIN<5:0>)--110111一一34MAMXFLLMaximum Frame Length Low Byte (MAMXFL<7:0>)00000000MAMXFLHMaximum Frame Length High Byte (MAMXFL<15:8>)000011034 MICMD一-一21一MIISCANMIIRD-----001119MIREGADR一一-MII Register Address (MIREGADR<4:0>)--0 000019MIWRLMII Write Data Low Byte (MIWR7:0>)00000000MIWRHMII Wirte Data High Byte (MIWR<15:8>)000019000019MIRDLMII Read Data Low Byte (MIRD<7:0>)00000000MIRDH19MII Read Data High Byte(MIRD<15:8>)0000 0000MAADR534MAC Address Byte 5 (MAADR<15:8>)0000000034 MAADR6MAC Address Byte 6 (MAADR<7:0>)0000000034MAADR3MAC Address Byte 3 (MAADR<31:24>), OUI Byte 30000000000000 000034 MAADR4MAC Address Byte 4 (MAADR<23:16>)34 MAADR100000000MAC Address Byte 1 (MAADR<47:40>), OUI Byte 134MAADR2MAC Address Byte 2 (MAADR<39:32>), OUI Byte 20000 0000EBSTSD0000000076Buit-in Self-Test Fl Seed (EBSTSD<7:0>)75EBSTCONPSV2PSV1PSVOPSELTMSEL1TMSELOTMEBISTST00000000EBSTCSLBuilt-in Self-Test Checksum Low Byte (EBSTCS7:0>)000000007676 EBSTCSHBuilt-in Self-Test Checksum High Byte (EBSTCS<15:8>)0000 0000MISTATBUSY21-一--rNVALIDSCAN0000----EREVID(2)--一Ethernet Revision ID (EREVID<4:0>)22--g qqqgECOCON(3)一一一COCON26一一COCON1COCONO.-10056EFLOCON一一FULDPXSFCEN1FCENO-000-一----EPAUSL000000057 Pause Timer Value Low Byte (EPAUS<7:0>)[EPAUSHPause Timer Value High Byte (EPAUS<15:8>)0001000057Legend:x = unknown, u = unchanged, - = unimplemented, q = value depends on condition,, r = reserved, do not modify.Note1:CLKRDYresetsto'o'onPower-onResetbutis unaffected on all otherResets2: EREVID is a read-only register.3:ECOCONresetsto'------1oo'onPower-onResetand----uuu'onall otherResetsPreliminaryDS39662C-page 142008 Microchip Technology Inc
ENC28J60 DS39662C-page 14 Preliminary © 2008 Microchip Technology Inc. EPMCSL Pattern Match Checksum Low Byte (EPMCS<7:0>) 0000 0000 51 EPMCSH Pattern Match Checksum High Byte (EPMCS<15:0>) 0000 0000 51 EPMOL Pattern Match Offset Low Byte (EPMO<7:0>) 0000 0000 51 EPMOH ó ó ó Pattern Match Offset High Byte (EPMO<12:8>) -0 0000 51 ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 48 EPKTCNT Ethernet Packet Count 0000 0000 43 MACON1 ó ó ó r TXPAUS RXPAUS PASSALL MARXEN -0 0000 34 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 35 MACON4 ó DEFER BPEN NOBKOFF ó ór r -000 -00 36 MABBIPG ó Back-to-Back Inter-Packet Gap (BBIPG<6:0>) -000 0000 36 MAIPGL ó Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) -000 0000 34 MAIPGH ó Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) -000 0000 34 MACLCON1 ó ó ó ó Retransmission Maximum (RETMAX<3:0>) - 1111 34 MACLCON2 ó ó Collision Window (COLWIN<5:0>) -11 0111 34 MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>) 0000 0000 34 MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>) 0000 0110 34 MICMD ó ó ó ó ó ó MIISCAN MIIRD - -00 21 MIREGADR ó ó ó MII Register Address (MIREGADR<4:0>) -0 0000 19 MIWRL MII Write Data Low Byte (MIWR<7:0>) 0000 0000 19 MIWRH MII Write Data High Byte (MIWR<15:8>) 0000 0000 19 MIRDL MII Read Data Low Byte (MIRD<7:0>) 0000 0000 19 MIRDH MII Read Data High Byte(MIRD<15:8>) 0000 0000 19 MAADR5 MAC Address Byte 5 (MAADR<15:8>) 0000 0000 34 MAADR6 MAC Address Byte 6 (MAADR<7:0>) 0000 0000 34 MAADR3 MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 0000 0000 34 MAADR4 MAC Address Byte 4 (MAADR<23:16>) 0000 0000 34 MAADR1 MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 0000 0000 34 MAADR2 MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 0000 0000 34 EBSTSD Built-in Self-Test Fill Seed (EBSTSD<7:0>) 0000 0000 76 EBSTCON PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST 0000 0000 75 EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) 0000 0000 76 EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) 0000 0000 76 MISTAT ó ó ó ó r NVALID SCAN BUSY - 0000 21 EREVID(2) ó ó ó Ethernet Revision ID (EREVID<4:0>) -q qqqq 22 ECOCON(3) ó ó ó ó ó COCON2 COCON1 COCON0 - -100 6 EFLOCON ó ó ó ó ó FULDPXS FCEN1 FCEN0 - -000 56 EPAUSL Pause Timer Value Low Byte (EPAUS<7:0>) 0000 0000 57 EPAUSH Pause Timer Value High Byte (EPAUS<15:8>) 0001 0000 57 TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Reset Details on Page Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify. Note 1: CLKRDY resets to ë0í on Power-on Reset but is unaffected on all other Resets. 2: EREVID is a read-only register. 3: ECOCON resets to ë- -100í on Power-on Reset and ë- -uuuí on all other Resets
ENC28J603.1.1ECON1REGISTERTheECON1register,shown in Register 3-1,isusedtocontrolthemainfunctionsoftheENC28J60.Receiveenable,transmitrequest,DMAcontrolandbankselectbitscanallbefound inECON1.REGISTER3-1:ECON1:ETHERNETCONTROLREGISTER1R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0RW-0R/W-0TXRSTRXRSTDMASTCSUMENTXRTSRXENBSEL1BSELObit 7bit oLegend:R=Readable bitW= Writable bitU= Unimplemented bit, read as'0'-n = Value at POR"1'= Bit is set"0' = Bit is clearedx= Bit is unknownbit 7TXRST: Transmit Logic Reset bit1=Transmit logic isheld inReset0=Normaloperationbit 6RXRST:ReceiveLogicResetbit1=Receive logic is held inReset0=Normaloperationsbit 5DMAST: DMA Start and Busy Status bitDMAcopyorchecksumoperation is in progress1=0=DMA hardware is Idlebit 4CSUMEN:DMAChecksumEnablebit1=DMAhardwarecalculateschecksumsO=DMAhardwarecopiesbuffermemorybit 3TXRTS: Transmit Request to Send bit1 = The transmit logic is attempting to transmit a packet0 = The transmit logic is Idlebit 2RXEN:ReceiveEnablebit1=Packets which pass thecurrentfilterconfiguration willbewriten into thereceive bufferO=All packetsreceivedwill beignoredbit 1-0BSEL1:BSELO:BankSelectbits11=SPIaccessesregisters in Bank310=SPlaccessesregistersinBank201=SPl accesses registers in Bank 100=SPlaccessesregisters inBank0PreliminaryDS39662C-page 15 2008 Microchip Technology Inc
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 15 ENC28J60 3.1.1 ECON1 REGISTER The ECON1 register, shown in Register 3-1, is used to control the main functions of the ENC28J60. Receive enable, transmit request, DMA control and bank select bits can all be found in ECON1. REGISTER 3-1: ECON1: ETHERNET CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXRST RXRST DMAST CSUMEN TXRTS RXEN BSEL1 BSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ë0í -n = Value at POR ë1í = Bit is set ë0í = Bit is cleared x = Bit is unknown bit 7 TXRST: Transmit Logic Reset bit 1 = Transmit logic is held in Reset 0 = Normal operation bit 6 RXRST: Receive Logic Reset bit 1 = Receive logic is held in Reset 0 = Normal operations bit 5 DMAST: DMA Start and Busy Status bit 1 = DMA copy or checksum operation is in progress 0 = DMA hardware is Idle bit 4 CSUMEN: DMA Checksum Enable bit 1 = DMA hardware calculates checksums 0 = DMA hardware copies buffer memory bit 3 TXRTS: Transmit Request to Send bit 1 = The transmit logic is attempting to transmit a packet 0 = The transmit logic is Idle bit 2 RXEN: Receive Enable bit 1 = Packets which pass the current filter configuration will be written into the receive buffer 0 = All packets received will be ignored bit 1-0 BSEL1:BSEL0: Bank Select bits 11 = SPI accesses registers in Bank 3 10 = SPI accesses registers in Bank 2 01 = SPI accesses registers in Bank 1 00 = SPI accesses registers in Bank 0
ENC28J603.1.2ECON2REGISTERThe ECON2 register,shown in Register 3-2, is used tocontrolothermainfunctionsoftheENC28J60.REGISTER 3-2:ECON2:ETHERNETCONTROLREGISTER2RW-0(1)U-OU-OU-OR/W-1RW-0R/W-0RW-0IAUTOINCPKTDECPWRSVVRPSbit 7bit oLegend:R = Readable bitW= Writable bitU= Unimplemented bit, read as '0'-n=ValueatPOR"1'=Bit is set'0'= Bit is clearedx=Bitisunknownbit 7AUTOINC:AutomaticBufferPointerIncrementEnablebit1=Automatically increment ERDPTorEWRPTon reading fromorwritingtoEDATA0=DonotautomaticallychangeERDPTandEWRPTafterthebufferisaccessedbit 6PKTDEC:PacketDecrementbit1=DecrementtheEPKTCNTregisterbyone0=Leave EPKTCNT unchangedbit 5PWRSV:PowerSaveEnablebit1 = MAC, PHY and control logic are in Low-Power Sleep mode0=Normaloperationbit 4Reserved: Maintain as'obit 3VRPS:Voltage Regulator Power Save Enable bitWhenPWRSV= 1:1=InternalvoltageregulatorisinLow-CurrentmodeO=Internal voltageregulatoris in Normal CurrentmodeWhen PWRSV = 0:Thebit is ignored; the regulator always outputs as much current as thedevice requiresbit 2-0Unimplemented:Read as‘o'Note 1:This bit is automatically cleared once it is set.PreliminaryDS39662C-page 162008 Microchip Technology Inc
ENC28J60 DS39662C-page 16 Preliminary © 2008 Microchip Technology Inc. 3.1.2 ECON2 REGISTER The ECON2 register, shown in Register 3-2, is used to control other main functions of the ENC28J60. REGISTER 3-2: ECON2: ETHERNET CONTROL REGISTER 2 R/W-1 R/W-0(1) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 AUTOINC PKTDEC PWRSV r VRPS ó ó ó bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ë0í -n = Value at POR ë1í = Bit is set ë0í = Bit is cleared x = Bit is unknown bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit 1 = Automatically increment ERDPT or EWRPT on reading from or writing to EDATA 0 = Do not automatically change ERDPT and EWRPT after the buffer is accessed bit 6 PKTDEC: Packet Decrement bit 1 = Decrement the EPKTCNT register by one 0 = Leave EPKTCNT unchanged bit 5 PWRSV: Power Save Enable bit 1 = MAC, PHY and control logic are in Low-Power Sleep mode 0 = Normal operation bit 4 Reserved: Maintain as ë0í bit 3 VRPS: Voltage Regulator Power Save Enable bit When PWRSV = 1: 1 = Internal voltage regulator is in Low-Current mode 0 = Internal voltage regulator is in Normal Current mode When PWRSV = 0: The bit is ignored; the regulator always outputs as much current as the device requires. bit 2-0 Unimplemented: Read as ë0í Note 1: This bit is automatically cleared once it is set
ENC28J603.2EthernetBuffer3.2.2TRANSMITBUFFERAny space within the 8-Kbyte memory, which is notThe Ethernet buffer contains transmit and receiveprogrammed as part of the receive FIFO buffer, ismemory used by the Ethernet controller. The entireconsidered to be the transmit buffer.The responsibilitybuffer is 8Kbytes,divided into separate receive andofmanagingwherepacketsarelocated inthetransmittransmit bufferspaces.The sizes andlocations ofbufferbelongstothehostcontroller.Wheneverthehosttransmitandreceivememoryarefullyprogrammablecontrollerdecidestotransmitapacket,theETXSTandby the host controller using the SPlinterface.ETXND Pointers are programmed with addressesThe relationship of the buffer spaces is shown inspecifying where, within the transmit buffer, the partic-Figure 3-2.ularpackettotransmitislocated.Thehardwaredoesnot check that the start and end addresses do not3.2.1RECEIVEBUFFERoverlap with thereceive buffer.Toprevent bufferThe receive buffer constitutes a circular FIFO buffercorruption,thehostcontrollermustmakesuretonotmanagedbyhardware.Theregisterpairs,transmit a packet while the ETXST and ETXNDERXSTH:ERXSTLandERXNDH:ERXNDL,serveasPointersareoverlappingthereceivebuffer,or whilethepointers to define the buffer's size and location withinETXNDPointer is too close tothereceivebuffer.Seethe memory.Thebytepointed to by ERXST and theSection7.1"TransmittingPackets"formorebyte pointed to byERXNDare both included in theinformation.FIFO buffer.3.2.3READING ANDWRITING TOAs bytes of data are received from the EthernetTHEBUFFERinterface,they are written intothe receive buffersequentially.However, after the memory pointed to byThe Ethernet buffer contents are accessed from theERXND is writtento,thehardwarewill automaticallyhostcontrollerthoughseparateReadandWritePoint-write the next byte of received data to the memoryers (ERDPT and EWRPT) combined with the readpointedto by ERXST.As a result, the receive hardwarebuffermemoryandwritebuffermemorySPIwill never write outside the boundaries of theFIFOcommands.While sequentially reading from thereceive buffer,a wrapping condition willoccur attheThe host controller may program the ERXST andend of thereceivebuffer.WhilesequentiallywritingtoERXNDPointerswhen thereceivelogic isnotenabledthe buffer, no wrapping conditions will occur. SeeThe pointers must not be modified while the receiveSection4.2.2"Read Buffer MemoryCommand"andlogic is enabled (ECON1.RXEN is set).If desired, theSection4.2.4"WriteBufferMemoryCommand"forPointers may span the 1FFFh to 000oh memorymore information.boundarythehardwarewill still operateas a FIFOTheERXWRPTH:ERXWRPTLdefineregistersa3.2.4DMAACCESSTOTHEBUFFERlocationwithintheFIFO wherethehardwarewill writeThe integrated DMAcontrollermustread fromthebufferbytes that it receives.The pointer is read-only and iswhen calculating a checksumand it must read and writeautomatically updated by the hardwarewhenever ato the buffer when copying memory.The DMA followsnew packet is successfully received.The pointer isthe same wrapping rules that SPl accesses do.While ituseful for determining how much freespaceissequentially reads, it will be subjectto a wrapping condi-available within the FIFO.tionattheendof thereceivebuffer.All writes itdoes willThe ERXRDPT registers define a location within thenot be subject to any wrappingconditions.SeeFIFO where the receivehardware is forbidden to writeSection13.0"DirectMemoryAccessController"forto.Innormaloperation,thereceivehardwarewillwritemore information.data up to, but not including, the memory pointed to byERXRDPT.If theFIFOfillsupwithdataandnewdatacontinuestoarrive,thehardwarewillnotoverwritethepreviously received data.Instead,the newdata will bethrown away and the old data will be preserved.Inordertocontinuouslyreceivenewdata.thehostcon-trollermust periodically advance this pointer wheneveritfinishes processingsome,orall,oftheoldreceiveddata.Preliminary 2008 Microchip Technology Inc.DS39662C-page 17
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 17 ENC28J60 3.2 Ethernet Buffer The Ethernet buffer contains transmit and receive memory used by the Ethernet controller. The entire buffer is 8 Kbytes, divided into separate receive and transmit buffer spaces. The sizes and locations of transmit and receive memory are fully programmable by the host controller using the SPI interface. The relationship of the buffer spaces is shown in Figure 3-2. 3.2.1 RECEIVE BUFFER The receive buffer constitutes a circular FIFO buffer managed by hardware. The register pairs, ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as pointers to define the bufferís size and location within the memory. The byte pointed to by ERXST and the byte pointed to by ERXND are both included in the FIFO buffer. As bytes of data are received from the Ethernet interface, they are written into the receive buffer sequentially. However, after the memory pointed to by ERXND is written to, the hardware will automatically write the next byte of received data to the memory pointed to by ERXST. As a result, the receive hardware will never write outside the boundaries of the FIFO. The host controller may program the ERXST and ERXND Pointers when the receive logic is not enabled. The pointers must not be modified while the receive logic is enabled (ECON1.RXEN is set). If desired, the Pointers may span the 1FFFh to 0000h memory boundary; the hardware will still operate as a FIFO. The ERXWRPTH:ERXWRPTL registers define a location within the FIFO where the hardware will write bytes that it receives. The pointer is read-only and is automatically updated by the hardware whenever a new packet is successfully received. The pointer is useful for determining how much free space is available within the FIFO. The ERXRDPT registers define a location within the FIFO where the receive hardware is forbidden to write to. In normal operation, the receive hardware will write data up to, but not including, the memory pointed to by ERXRDPT. If the FIFO fills up with data and new data continues to arrive, the hardware will not overwrite the previously received data. Instead, the new data will be thrown away and the old data will be preserved. In order to continuously receive new data, the host controller must periodically advance this pointer whenever it finishes processing some, or all, of the old received data. 3.2.2 TRANSMIT BUFFER Any space within the 8-Kbyte memory, which is not programmed as part of the receive FIFO buffer, is considered to be the transmit buffer. The responsibility of managing where packets are located in the transmit buffer belongs to the host controller. Whenever the host controller decides to transmit a packet, the ETXST and ETXND Pointers are programmed with addresses specifying where, within the transmit buffer, the particular packet to transmit is located. The hardware does not check that the start and end addresses do not overlap with the receive buffer. To prevent buffer corruption, the host controller must make sure to not transmit a packet while the ETXST and ETXND Pointers are overlapping the receive buffer, or while the ETXND Pointer is too close to the receive buffer. See Section 7.1 ìTransmitting Packetsî for more information. 3.2.3 READING AND WRITING TO THE BUFFER The Ethernet buffer contents are accessed from the host controller though separate Read and Write Pointers (ERDPT and EWRPT) combined with the read buffer memory and write buffer memory SPI commands. While sequentially reading from the receive buffer, a wrapping condition will occur at the end of the receive buffer. While sequentially writing to the buffer, no wrapping conditions will occur. See Section 4.2.2 ìRead Buffer Memory Commandî and Section 4.2.4 ìWrite Buffer Memory Commandî for more information. 3.2.4 DMA ACCESS TO THE BUFFER The integrated DMA controller must read from the buffer when calculating a checksum and it must read and write to the buffer when copying memory. The DMA follows the same wrapping rules that SPI accesses do. While it sequentially reads, it will be subject to a wrapping condition at the end of the receive buffer. All writes it does will not be subject to any wrapping conditions. See Section 13.0 ìDirect Memory Access Controllerî for more information
ENC28J60FIGURE3-2:ETHERNETBUFFERORGANIZATIONTransmit Buffer Start0000h+(ETXSTH:ETXSTL)Buffer Write Pointer-Transmit Buffer DataAAh4(EWRPTH:EWRPTL)(WBM AAh)TransmitBufferTransmit BufferEnd(ETXNDH:ETXNDL)+ReceiveBufferStart(ERXSTH:ERXSTL)ReceiveBuffer(Circular FIFO)BufferReadPointerReceiveBufferData55h(ERDPTH:ERDPTL)(RBM 55h)ReceiveBufferEnd1FFFh(ERXNDH:ERXNDL)PreliminaryDS39662C-page 18 2008 Microchip Technology Inc
ENC28J60 DS39662C-page 18 Preliminary © 2008 Microchip Technology Inc. FIGURE 3-2: ETHERNET BUFFER ORGANIZATION Transmit Buffer 0000h 1FFFh Transmit Buffer Start (ETXSTH:ETXSTL) Transmit Buffer End (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) Receive Buffer End (ERXNDH:ERXNDL) Receive Buffer Buffer Write Pointer (EWRPTH:EWRPTL) AAh Transmit Buffer Data (WBM AAh) Buffer Read Pointer (ERDPTH:ERDPTL) Receive Buffer Data (RBM 55h) (Circular FIFO) 55h