29.6Register Description2129.6.1RegisterMapARM092019-4-9
29.6 Register Description ARM09 2019-4-9 21 29.6.1 Register Map
29.6.1RegisterMap22RegisterOffsetResetValueDescription0x0XI2CCONn0x0000Specifiesthe12C-businterface0controlregister0x0012CSTATn0x0004Specifiesthe12C-bus interface0control/statusregister0x0008OxXX12CADDnSpecifies the 12C-bus interface0 address registerSpecifies theI2C-bus interface0 transmit/receivedata0xXX12CDSn0x000Cshift registerSpecifies the12C-bus interface0 multi-masterline0x00100x0012CLCncontrol registerARM092019-4-9
29.6.1 Register Map ARM09 2019-4-9 22
29.6.1.1 12CCONn (n = 0 to 7)23ARMO92019-4-9
29.6.1.1 I2CCONn (n = 0 to 7) ARM09 2019-4-9 23
BitTypeNameDescriptionResetValue0-RSVD[31:8]Reserved12C-bus acknowledge enable bit0=DisablesAcknowledge0[7]RW1=Enablesgeneration(1)InTxmode,theI2CSDA is idle in theACK timeInRxmode,theI2CSDAislowintheACKtimeSourceclockof2C-bustransmitclockprescalerselection bitTx clock source0[6] RWselection0=12CCLK=fPCLK/161=12CCLK=fPCLK/512I2C-bus Tx/Rx interruptenable/disablebit0Tx/Rx Interrupt (5)[5]RW0=Disables1=EnablesI2C-busTx/Rx interruptpendingflagYoucannotwritethisbitto1.If you read this bitas1,theI2CSCListiedtoLowandtheI2CisstoppedToresumetheoperation,writethisbitas0Interrupt pending flag0=1) No interrupt ispending (If Read)S0[4] (2) (3)2)Clears pendingcondition andresumestheoperation(lfWrite).1=1)Interrupt ispending(IfRead)2)N/A (If Write)2C-bustransmitclockprescaler4-bitprescalervaluedeterminesthe12C-busTransmitclockvalueRW[3:0]transmit clock frequency according to theformula-(4)24given here:Txclock=12CCLK/(I2CCON[3:0]+1)
24 ARM09 2019-4-9
29.6.1.2 12CSTATn (n = 0 to 7)25ARMO92019-4-9
29.6.1.2 I2CSTATn (n = 0 to 7) ARM09 2019-4-9 25