29.3 BlockDiagram1612CADDAddress Register全ComparatorI2C-Bus Control Logic+SCL12CCON12CSTATPCLK4-bit PrescalerShift RegisterSDA4ShiftRegister(I2CDS)?Data BusFigure29-112C-BusBlockDiagramARM092019-4-9
29.3 Block Diagram ARM09 2019-4-9 16 I2CADD
29.4Interface Operation The operation modes are: Master TransmitterMode MasterReceive Mode Slave Transmitter ModeSlaveReceive ModeARMO92019-4-9
29.4 Interface Operation ARM09 2019-4-9 17 The operation modes are: Master Transmitter Mode Master Receive Mode Slave Transmitter Mode Slave Receive Mode
29.4InterfaceOperation(cont)18 The relationships among operation modes:StartandStopconditionsDatatransferformatACKsignaltransmission Read-Write operationBusarbitrationproceduresAbortconditions Configuring lIC-busARM092019-4-9
29.4 Interface Operation (cont) ARM09 2019-4-9 18 The relationships among operation modes: Start and Stop conditions Data transfer format ACK signal transmission Read-Write operation Bus arbitration procedures Abort conditions Configuring IIC-bus
29.4InterfaceOperation(cont)1929.4.1 Start and Stop Conditions 29.4.2 Data Transfer Format 29.4.3 ACK Signal Transmission 29.4.4 Read-Write Operation 29.4.5Bus Arbitration Procedures 29.4.6 Abort Conditions 29.4.7 Configuring 12C-Bus29.4.8 Flowcharts of OperationsARMO92019-4-9
29.4 Interface Operation (cont) ARM09 2019-4-9 19 29.4.1 Start and Stop Conditions 29.4.2 Data Transfer Format 29.4.3 ACK Signal Transmission 29.4.4 Read-Write Operation 29.4.5 Bus Arbitration Procedures 29.4.6 Abort Conditions 29.4.7 Configuring I2C-Bus 29.4.8 Flowcharts of Operations
29.51/ODescription20VOPadSignalTypeDescription12C0_SCLmuxedInput/OutputI2C-businterface0serial clock lineXI2C0SCL12C0_SDAInput/OutputI2C-bus interface0serial data lineXI2COSDAmuxed12C1_SCLXI2C1SCLInput/OutputI2C-businterface1serialclocklinemuxedI2C1_SDAInput/OutputI2C-bus interface1serialdata lineXI2C1SDAmuxed12C2_SCLXuRTSn_1Input/OutputI2C-businterface2serial clock linemuxedI2C2_SDAXuCTSn_1Input/OutputI2C-bus interface2serialdata linemuxed12C3_SCLXuRTSn_2Input/Output12C-bus interface3serial clock linemuxedI2C3_SDAInput/Output12C-bus interface3serialdata lineXuCTSn_2muxed12C4_SCLInput/OutputI2C-businterface4serial clock lineXspiMOSI_0muxedI2C4_SDAInput/OutputI2C-bus interface4 serial data lineXspiMISO_0muxed12C5_SCLInput/OutputI2C-bus interface5serialclock lineXspiMOSI_1muxed12C5_SDAInput/Output12C-bus interface5 serialdata lineXspiMISO_1muxed12C6_SCLXi2s2SDOInput/Output12C-bus interface6serialclock linemuxedI2C6_SDAInput/Output12C-bus interface6 serial data lineXi2s2SDImuxed12C7_SCLXpwmTOUT_3Input/Output12C-bus interface7serialclock linemuxed12C7_SDAInput/Output2C-bus interface7serial data lineXpwmTOUT2muxed
29.5 I/O Description ARM09 2019-4-9 20