BitNameTypeReset ValueDescription0[31:8]RSVDReserved-I2C-bus Master/SlaveTx/Rxmode select bits00 = Slave receive mode[7:6] RWX00Mode selection01=Slavetransmitmode10=Masterreceivemode11=MastertransmitmodeI2C-bus busy signal status bitO= (Read)Not busy (If Read)Busy signal(write)STOP signalgenerationS0status/STARTSTOP[5] 1= (Read)Busy (IfRead)condition(write)STARTsignalgenerationTransfers the data in I2CDSautomatically just afterthestart signalI2C-busdata output enable/disablebits0[4] Serial output0=DisablesRx/Tx1=EnablesRx/TxI2C-bus arbitrationprocedure status flagbitRO0[3] Arbitration status flagO=Busarbitration successful1=Bus arbitrationfails duringserial /OI2C-bus address-as-slave status flag bitAddress-as-slaveO=Clearswhen it detects START/STOPcondition0[2] ROstatus flag1=Receivesslaveaddress thatmatches theaddressvalueintheI2CADDI2C-bus address zero status flag bitAddress zero status0RO[1]O=Clears when it detects START/STOP conditionflag1=Receivedslaveaddressis00000000bI2C-bus last-received bit status flag bitLast-received bitO=Last-receivedbit issettoO (receivesACK)[0]RO026statusflag1 = Last-received bit is set to 1 (does not receiveACK)
26 ARM09 2019-4-9
29.6.1.312CADDn(n=0to7)27BitNameTypeDescriptionResetValue0RSVD[31:8]Reserved7-bitslaveaddress,latchedfromthe12C-bus.Whenserialoutputenable=0inthe12CSTATI2CADDiswrite-enabled.TheI2CADDvalueis[7:0]RWXSlaveaddressRead any time,regardless of the current serialoutputenablebit(I2CSTAT)setting.Slave address: [7:1]Not mapped: [0]ARM092019-4-9
29.6.1.3 I2CADDn (n = 0 to 7) ARM09 2019-4-9 27
29.6.1.412CDSn (n=0to 7)28BitNameTypeResetValueDescriptionRSVD0[31:8]Reserved-8-bitdata shiftregisterforI2C-busTx/Rxoperation.Whenserialoutputenable=1intheI2CSTAT[7:0]RWXData shiftI2CDSiswrite-enabled.TheI2CDSvalueisReadanytime,regardlessofthecurrentserialoutputenablebit(I2CSTAT)setting.ARM092019-4-9
29.6.1.4 I2CDSn (n = 0 to 7) ARM09 2019-4-9 28
29.6.1.512CLCn (n=0to7)29Specifies the I2C-bus interfaceO multi-master line control registerBitNameTypeDescriptionResetValue0RSVD[31:27]Reserved12C-busfilterenablebitWhenSDAportisoperatingasinput,setthisbittoHigh.Thisfilterpreventserrorcausedbyglitch[2] RW0FilterenablebetweentwoPCLKclocksO=DisablesFilter1=EnablesFilterI2C-busSDAlinedelaylengthselectionbitsTheI2CcontrollerdelaystheSDA linebyfollowingclock cycle:[1:0]RW00SDAoutputdelay00=0clock01=5clocks10=10clocks11=15clocksARM092019-4-9
29.6.1.5 I2CLCn (n = 0 to 7) ARM09 2019-4-9 29 Specifies the I2C-bus interface0 multi-master line control register
29.7 Touch Screen30ARM092019-4-9
29.7 Touch Screen ARM09 2019-4-9 30