12CADDAddressRegister全ComparatorI2C-BusControl Logic全SCL12CCON12CSTATShiftRegisterPCLK4-bitPrescaleSDA全ShiftRegister(2CDS)4Data Bus12c-BusBlockDiagramFigure29-1SCL (Serial Clock Line) and SDA (Serial Data Line) for bi-directional transmissionIfI2C-busisidle,bothSDAandSCLlinesshouldbeatHighlevelHigh-to-Low transition of SDAinitiates a Start conditionLow-to-High transition of SDA initiates a Stop condition, if SCL is High11ARM092019-4-9
11 ARM09 2019-4-9 I2CADD SCL (Serial Clock Line) and SDA (Serial Data Line ) for bi-directional transmission If I2C-bus is idle, both SDA and SCL lines should be at High level High-to-Low transition of SDA initiates a Start condition Low-to-High transition of SDA initiates a Stop condition, if SCL is High
12CADDAddressRegister全ComparatorI2C-BusControl Logic全SCL12CCONI2CSTATPCLKShift RegisterSDA4-bitPrescaler全ShiftRegistep(12CDS)生Data BusFigure29-1_-12c-BusBlockDiagramThefront7bitsonSDAaretheaddress of slavedeviceThe 8thbitdeterminestransferdirection(Reador Write)12ARM092019-4-9
12 ARM09 2019-4-9 I2CADD The front 7 bits on SDA are the address of slave device The 8th bit determines transfer direction (Read or Write)
12CADDAddressRegister全ComparatorI2C-Bus Control Logic全SCLI2CCONI2CSTATPCLKShift Register4-bitPrescalerSDA全ShiftRegiste(2CDS)全Data BusFigure 29-112C-BusBlockDiagram-.EverydatabyteonSDAlineshouldbe8bitsThere is no limit eitherto sendorreceivebytesI2Cmaster and slave devices always send data from MSB first, andthen ACK bit immediatelyfollows everybyte13ARM092019-4-9
13 ARM09 2019-4-9 I2CADD Every data byte on SDA line should be 8 bits There is no limit either to send or receive bytes I2C master and slave devices always send data from MSB first, and then ACK bit immediately follows every byte
12CADDAddress Register全ComparatorI2C-BusControl Logic全SCL12CCON12CSTATPCLKShift RegisterSDA4-bitPrescaler?ShiftRegister(12CDS)4Data BusFigure29-1I2C-BusBlockDiagramTo-control multi-master 12G-bus operations by registers:12CCON(control),I2CSTAT(control/status)12CDS (Tx/Rx data shift), I2CADD (address)14ARM092019-4-9
14 ARM09 2019-4-9 I2CADD To control multi-master I2C-bus operations by registers: I2CCON (control), I2CSTAT (control/status) I2CDS (Tx/Rx data shift), I2CADD (address)
29.2Features15 9channelsmulti-master/slaveI2Cbusinterfaces 7-bit addressing mode Serial, 8-bit, and bi-directional data transfer100kbit/sinStandardmode 400kbit/sinFastmodeMaster/slavetransmit/receiveoperationsSupportsinterruptorpollingeventsARMO92019-4-9
29.2 Features ARM09 2019-4-9 15 9 channels multi-master/slave I2C bus interfaces 7-bit addressing mode Serial, 8-bit, and bi-directional data transfer 100 kbit/s in Standard mode 400 kbit/s in Fast mode Master/slave transmit/receive operations Supports interrupt or polling events