Peripheral BUSTransmitterTransmit FIFO Register(FIFO mode)Transmit Buffer RegisterTransmitHoldingRegister(Non-FIFO mode)Transmit Shifter★ TXDn---.ControlBuad-rateClock SourceUnitGeneratorReceiverMS+RXDnReceive ShifteramsungReceive Holding Register(Non-FIFO mode only)Receive Buffer RegisterReceive FIFO Register(FIFO mode)InFIFOmode,allbytesof BufferRegisterareusedasFIFOregister.In non-FIFO mode, only 1 byte of Buffer Register is used as Holding register.6ARMO92019-4-9Figure 28-1BlockDiagramofUART
6 ARM09 2019-4-9
2912CInter-lntegrated Circuit
29 I2C Inter-Integrated Circuit
2912C 29.1 Overview29.2 Features29.3BlockDiagram 29.4 Interface Operation29.51/ODescription29.6 RegisterDescription 29.7 Touch Screen29.8 SummaryARM092019-4-9
29 I2C ARM09 2019-4-9 8 29.1 Overview 29.2 Features 29.3 Block Diagram 29.4 Interface Operation 29.5 I/O Description 29.6 Register Description 29.7 Touch Screen 29.8 Summary
29.1OverviewARM092019-4-9
29.1 Overview ARM09 2019-4-9 9
12CADDAddressRegister全ComparatorI2C-BusControl Logic全SCL12CCON12CSTATShiftRegisterPCLKSDA4-bitPrescaler全ShiftRegister(2CDS)全Data BusFigure29-1I2C-BusBlockDiagramExynoshasfourI2CbusinterfacesArbitration controls multi-master/slave transferMaster cores initiate/terminate data transfer10ARM092019-4-9
10 ARM09 2019-4-9 I2CADD Exynos has four I2C bus interfaces Arbitration controls multi-master/slave transfer Master cores initiate/terminate data transfer