New Design Wizard Specify additional information about the new Synthesis tool Synopsys FPGA Express D: \Synopsys \FPGA_Express\bin-win32i Implementation tool Xilinx Foundation Default Family: XC4000E Block Diagram HDL )图多分 Default HDL Language:mmL 〈上一步⑩)下一步0取消
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esTc 设计中 Because we are not using synthesis and implementation tools in this lab, you can leave Synthesis tool and Implementation tool settings unchanged Set Block Diagram Configuration to HDL and Default HDL Language to HDL” Click on the next button to advance to the next page
设计中心 • Because we are not using synthesis and implementation tools in this lab, you can leave Synthesis tool and Implementation tool settings unchanged • Set Block Diagram Configuration to ”HDL” and Default HDL Language to ”VHDL” • Click on the Next button to advance to the next page
New Design Wizard Specify basic information about the new Type the design name study select the location of the design folder B rowse The name of the default working library of tudy The name specified here will be used as the &: file name for the library files and as the 1A7 9 logical name of the library. You can change 〈上一步)下一步0)取
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esTc 设计中 o In the Type the design name field, enter Your Design name, example: study Leave default values in the select the location of the design folder box and the The name of the default working library of the design box Click on the next button to advance to the next page Click Finish in the last window of the wizard
设计中心 • In the Type the design name field, enter Your_Design_name, example: study • Leave default values in the Select the location of the design folder box and the The name of the default working library of the design box • Click on the Next button to advance to the next page • Click Finish in the last window of the Wizard
O Active-HDL 4.2 Chappy)- Design Flow Manager File Edit Search View Design Simulation Tools Help e,》x Design Browser op-Level selection functional Unsorted HDE FSM BDI optIoN simulation 香 happy Add New File M happy library ptions b? post-synthesis-+ reports synthesis options simulation reports implementation options sImulation design flow B Files F Stru.QRes./.g Console 7 NUM INS
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