第6章宏功能模块应用6.1流水线乘法累加器设计MULTOclockCLKOLTITSUM15.0]dataalz.01sultl15.0databiz.01mutiplicatiorthADDEROO21台dataal150lesultr15.01clockEA+Edatab/15.0]1lo 2eoninst:MULTOclockdataalz.01OTPTTou15.0DATAa(7.0]atab[7.0DATAb[7.0]图6-1流水线乘法累加器顶层设计6.1.2电路结构与工作原理1.调用乘法器SymholLibraries:d/altera60/quartus60/ibraies/MegaWizard Plug-In Manager [page 1]TheMegawizardPluginManagerhelpsy00designflesthatcontancustomvariationsofmegafunctioWhicdo youwant toperfom?0Createanew.custommegalunctionvanalionCEdtan existing.custommeoafunctionvariatiorhenvanshnpuicht21991-2006AteaCorporatiocmRepeat-insertmodeanInseltsymbolasbleCarncel图6-2定制新的宏功能块1
1 第 6 章 宏功能模块应用 6.1 流水线乘法累加器设计 6.1.1 电路结构与工作原理 图 6-1 流水线乘法累加器顶层设计 6.1.2 电路结构与工作原理 1. 调用乘法器 图 6-2 定制新的宏功能块
xMegawizard Plug-In Manager [page 2a]Which megafunction would you like to customize?Which device family will you beCyclone ll一using?Select a megafunction from the list belowWhich type of output file do you want to create?InstalledPlug-Ins4AlteraSOPCBuilderCAHDLArithmeticOVHDLALTACCUMULATEE5Verilog HDLALTFP_ADD_SUB?ALTFP_MULTBrowse....What name do you want for the qutput file?ALTMEMMULTD:MULADDMULTOALTMULT_ACCUM (MAC)ALTMULT_ADDALTSQRTGenerate clearbox netlist file instead of a default wrapper fileLPM_ABS[fotusewith supported EDA synthesis tools onl)]LPM_ADD_SUBRetun tothispagefor another createoperationLPMCOMPARELPMCOUNTERNote:Tocompileaprojectsuccessfully intheQuartusllsoftwareyour design files must be in the project directory.in the global userLPM_DIVIDElibranes specified in the Options dialog box (Toolsmenul,or a userLPM MULTlibrayspecifiedin the User Libraries pageoftheSettings dialogPARALLELADDbox (Assignments menu)GatesYour cunent user library directories are由1/0xMegawizardPlug-InMaMULT[page1of5]DNM:LPM MULTVersion 6.0AboutDocumentationParameter2sinBsunmaySettingsLtatGeneral>PipeliningSeneral2Multiplier configurationMULTOMultiplydataa inputby'databinputdataa[7.0]Multiply'dataainput by itself (squaring operation)resut[15.0]Ttedatab[7.0]multiplioation8How wide should the'dataa'input bus be?bits8bitsHow wide should the'datab'input bus be?Create a'sum'input bus withawidth ofVbitsHow should the width of the'result'output be determined?OAutomatically calculate the width16Restrictthe widthtovbitsResource Usage117lutCancel<BackNext >Finish图6-4设置乘法器参数2
2 图 6-3 选择 LPM 宏功能模块 图 6-4 设置乘法器参数
Does the'datab'input bus have a constant value?MULTOONocataa[7.0]0Yes,the value isesut[15.0]datab[7.0]Which type of multiplication do you want?UnsignedSignedWhichmultiplier implementation should be used?Use the default implementation Use dedicated multiplier circuitry (Not available for all families)OUselogicelementsDo you want to pipeline the function?MULTOONoclock2O Yes, I want an output latency ofclock cyclesdataa[7..0]resut[15.0]Create an asynchronous Clear inputdatab[7..0]sionemultiplicatiorCreate a Clock Enable inputWhich type of optimizationdo you want?DefaultOSpeedOAreaXMegawizard Plug-InMLPM_ADD_SUB[page1of6]LPMADDSUB艺Version 6.0AboutDocumentation2.调Parameter2535maryLibrarySettingsHGeneralGeneral2PortsPipeliningVCurrently selected device family:Cyclone IIADDEROdataa[15.0]resu15.01How wide should the'data and'datab'input buses be?16 bits+datab[15.0]Which operating mode do you want for the addet/subtractor?Addition.onlySubtraction onlyCreate an 'add sub'input port to allow me to do both(1 adds; 0 subtracts)n
3 图 6-5 设置乘法器结构类型 图 6-6 将 LPM 乘法器设置为流水线工作方式 2. 调用加法器和锁存器
ADDEROdataa[15.0]Is the'dataa'or'datab'input bus value a constant?resut[15.0]A+BONo,both yalues varydatab[15..0]Yes, dataa=Yes, datab ADDERODo you want any optional inputs or outputs?dataa[15.0]Input:resut[15.0]Createa carry inputdatabl15.0]OutputscoutCreate a Carry outputCreateanoverflowoutputADDERODo you want to pipeline the function?dataa[15..0]clockresut[15.0]Nodatab[15.0]Yes,I want an output latencyofClock cyclescoutCreate an asynchronous Clear nputCreate a Clock Enable inputLPMFFVersion 6.0AboutDocumentationParameter2SimulationsummarySettingsLibraryPageGeneralOptional Inputs8How many flipflops do you want?REGODFFdata[7.0]whichtype of flipflops do youwant?>clockq[7.0]ODFflipflopTflipflopUse'data' input port (acts as abitwise enableifno load signal isused)Create a Clock Enable input4
4 图 6-7 设置 LPM 加法器类型 图 6-8 选择加法器数据输入类型 图 6-9 为加法器增加进位输出 图 6-10 为加法器增加流水线功能
Successful - Thu AueFlow StatusQuartus II Version6.0Bui1d20206/20MULTADDRevision Name6.1.3电路Top-level Entity HameMULTADDFamilyCyelone IIDeviceEP2C8Q208C8FinalTiming ModelsYesMet timing requirements223/8,256（38）Total logic elements127Total registers34/138（25%）Total pins0Total virtual pins0/165,888（0%)Total memory bitsEmbedded Multiplier 9-bit elements0/36(0%）Total PLLs0/2(0%)MULTADD.dfCompilation Report-Timing Analyzer Sum...Timing Analyzer SummaryCompilation Report鲁旨 Legal NoticeRequiredActualSlackTypeFromTimeTimeFlowSummary1N/ADATAb[2]Worst-case tsuNone10.350nsFlowSettingsEEFlowNon-DefautGlobal S2N/A9.806nsADDEROinWorst-case tcoNoneFlowElapsedTime3N/ADATAa[14]Worst-case thNone-1.231 ns自FlowLogN/AClock Setup: CLK'None140.90 MHz [ period = 7.097 ns ) MULT0:instEAnalysis &SynthesisSTotal number of failed paths由营FitterAssembler Timing Analyzer5SummarySettingsSirMULTADD.bdfCompilation Report·TimingA...MULTADD.wf三Timing Analyzer SummalCompilation Report鲁旨 Legal NoticeRequredActualSlackTypeFromTimeTimeEFlowSummaryAWorst-case tsuN/A8.809nsDATAa[NoneFlowSettingsFlowNon-Defaut Global2N/ANone8.981nsADDERWorst-case tcoFlowElapsed Time3Worst-case thN/ANone0.829 nsDATAbl雪FlowLogN/AClock Setup.'CLKNoneRestricted to 180.57MHz(period =5.538 ns)REG0:irREAnalysis &Synthesis5Total numberoffailed paths台FitterO巨Assembler Timing AnalyzerS具SummarySettingsClockSettingsSumm5
5 图 6-11 为 LPM 寄存器选择 D 触发器类型 6.1.3 电路时序仿真与测试 图 6-12 基于逻辑宏单元的设计报告 图 6-14 基于逻辑宏单元的流水线乘法累加器时序分析报告