技术EDA第3章VHDL 基础
EDA 技 术 第3章 VHDL 基础
3.1 VHDL基本语法3.1.1组合电路描述amux21aay6sb图3-2mux21a结构体图3-1mux21a实体
3.1 VHDL 基本语法 3.1.1 组合电路描述 图3-1 mux21a实体 图3-2 mux21a结构体
3.1 VHDL基本语法3.1.1组合电路描述【例3-1】ENTITY mux21a ISPORT （a,b:INBIT;INBIT;s：Y : OUTBIT) ;ENDENTITYmux2la;OFmux21aISARCHITECTUREOneBEGIN10:bWHENs=ELSEy<=aENDARCHITECTUREone;
3.1 VHDL 基本语法 3.1.1 组合电路描述 【例3-1】 ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN y <= a WHEN s = '0' ELSE b ; END ARCHITECTURE one ;
3.1 VHDL基本语法3.1.1组合电路描述【例3-2】ENTITY mux21aISPORT（a,b,s:INBIT;Y :OUT BIT);END ENTITY mux21a;ARCHITECTURE One OF mux21a ISSIGNAL d,e :BIT;BEGINd <= a AND(NOT S)e<= b ANDY<=dOR:se;ENDARCHITECTUREone
3.1 VHDL 基本语法 3.1.1 组合电路描述 【例3-2】 ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGIN d <= a AND (NOT S) ; e <= b AND s ; y <= d OR e ; END ARCHITECTURE one ;
3.1 VHDL基本语法3.1.1组合电路描述【例3-3】ENTITY mux21a ISINPORT（a,b,s:BIT;Y : OUT BIT)END ENTITY mux21a;OF mux21aIsARCHITECTUREoneBEGINPROCESS(a,b,s)BEGIN-0-IFS=THENELSEy<=b;y<=a:ENDIF;ENDPROCESS;END ARCHITECTUREone
3.1 VHDL 基本语法 【例3-3】 ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN PROCESS (a,b,s) BEGIN IF s = '0' THEN y <= a ; ELSE y <= b ; END IF; END PROCESS; END ARCHITECTURE one ; 3.1.1 组合电路描述