Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.(进程的逻辑 地址空间可能是不连续的,如果有可用的物理内存,它将分给进程。) Divide physical memory into fixed-sized blocks called frames (size is power of2, between512 bytes and8192 bytes).(把物理内存分成大小固 定的块 ° Divide logical memory into blocks of same size called pages.(把逻辑内 存也分位固定大小的块,叫做页。) Keep track of all free frames.(保留一个页的记录。) e To run a program of size n pages, need to find n free frames and load program(运行一个有N页大小的程序,需要找到N个空的页框读入程序。) Set up a page table to translate logical to physical addresses.(建立一 个页表,把逻辑地址转换为物理地址。) nternal fragmentation.(内碎片。 Applied Operating System Concepts 9.16 Silberschatz, Galvin, and Gagne @1999
Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts 9.16 Paging • Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.（进程的逻辑 地址空间可能是不连续的，如果有可用的物理内存，它将分给进程。） • Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).（把物理内存分成大小固 定的块。） • Divide logical memory into blocks of same size called pages.（把逻辑内 存也分位固定大小的块，叫做页。） • Keep track of all free frames.（保留一个页的记录。） • To run a program of size n pages, need to find n free frames and load program.（运行一个有N页大小的程序，需要找到N个空的页框读入程序。） • Set up a page table to translate logical to physical addresses. （建立一 个页表，把逻辑地址转换为物理地址。） • Internal fragmentation.（内碎片。）
Address translation scheme Address generated by CPU is divided into(cPU产生的地址被 分为) table which contains base address of each page in age Page number(p)(页号)一 used as an index into a physical memory.(它包含每个页在物理内存中的基址,用 来作为页表的索引。) Page offset(d)(RB)-combined with base address to define the physical memory address that is sent to the memory unit.(同基址相结合,用来确定送入内存设备的物 理内存地址。) Applied Operating System Concepts 9.17 Silberschatz, Galvin, and Gagne @1999
Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts 9.17 Address Translation Scheme • Address generated by CPU is divided into（CPU产生的地址被 分为）: – Page number (p) （页号）– used as an index into a page table which contains base address of each page in physical memory.（它包含每个页在物理内存中的基址，用 来作为页表的索引。） – Page offset (d) （偏移）– combined with base address to define the physical memory address that is sent to the memory unit.（同基址相结合，用来确定送入内存设备的物 理内存地址。）
Address Translation Architecture logical physical address address CPU d phys memory page table Applied Operating System Concepts 9.18 Silberschatz, Galvin, and Gagne @1999
Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts 9.18 Address Translation Architecture
Paging Example frame number page O page 1 1 page 0 page 2 0123 page 3 page table 3 page 2 page 1 memory 5 6 7 page 3 physical memory Applied Operating System Concepts 9.19 Silberschatz, Galvin, and Gagne @1999
Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts 9.19 Paging Example
Implementation of Page Table Page table is kept in main memory.(主存中的页表) Page-table base register(PTBR) points to the page table. (A 表基址寄存器指向页表) Page-table length register(PRLR) indicates size of the page table.(页表限长寄存器表明页表的长度) e In this scheme every datalinstruction access requires two memory accesses. One for the page table and one for the data/instruction.(在这个机制中,每一次的数据指令存取需要两 次内存存取,一次是存取页表,一次是存取数据) The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers(TLBs).(通过一个联 想寄存器,可以解决两次存取的问题) Applied Operating System Concepts Silberschatz, Galvin, and Gagne @1999
Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts 9.20 Implementation of Page Table • Page table is kept in main memory.（主存中的页表） • Page-table base register (PTBR) points to the page table.（页 表基址寄存器指向页表） • Page-table length register (PRLR) indicates size of the page table.（页表限长寄存器表明页表的长度） • In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.（在这个机制中，每一次的数据/指令存取需要两 次内存存取，一次是存取页表，一次是存取数据） • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs). (通过一个联 想寄存器，可以解决两次存取的问题）