8. Main Memory ●●● ●●●● ●●●●● ●●●● ●●0●● Objectives ●●●0 ●●●● o To provide a detailed description of various ways f organizing memory hardware To discuss various memory-management techniques, including paging and segmentation o To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging
2 8. Main Memory ⚫ Objectives ⚫ To provide a detailed description of various ways of organizing memory hardware ⚫ To discuss various memory-management techniques, including paging and segmentation ⚫ To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging
●●● 8. Main Memory ●●●● ●●●●● ●●●● 8.1 Background ●●0●● ●●●● ●●●● 8.2 Swapping 8.3 Contiguous Memory Allocation o8.4 Paging 8.5 Structure of the Page Table ●86 Segmentation e8. 7 Example: The Intel Pentium
3 8. Main Memory ⚫ 8.1 Background ⚫ 8.2 Swapping ⚫ 8.3 Contiguous Memory Allocation ⚫ 8.4 Paging ⚫ 8.5 Structure of the Page Table ⚫ 8.6 Segmentation ⚫ 8.7 Example: The Intel Pentium
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Memory is central to the operation of a. ●●●● modern computer system o Main memory and registers are only storage CPU can access directl Program must be brought (from disk) into memory e Instruction-execution cycle CPU fetches an instruction from memory according to the value of the program counter o The instruction is then decoded and may cause operands to be fetch from memory After the instruction has been executed the results may be stored back in memory
4 8.1 Background ⚫ Memory is central to the operation of a modern computer system ⚫ Main memory and registers are only storage CPU can access directly ⚫ Program must be brought (from disk) into memory ⚫ Instruction-execution cycle ⚫ CPU fetches an instruction from memory according to the value of the program counter ⚫ The instruction is then decoded and may cause operands to be fetch from memory ⚫ After the instruction has been executed, the results may be stored back in memory
8. 1 Background ●●● ●●●● ●●●●● ●●●● Speed of accessing memory ●●0●● ●●●0 Register access in one cycle of CPU clock o Main memory access can take many cycles o Cache sits between main memory and CPU registers to accommodate a speed difference
5 8.1 Background ⚫ Speed of accessing memory ⚫ Register access in one cycle of CPU clock ⚫ Main memory access can take many cycles ⚫ Cache sits between main memory and CPU registers to accommodate a speed difference
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Memory address ●●●0 ●●●● e Memory consist of a larger array of words or bytes, each with its own address We do ignore how a program generates a memory address o We are interested only in the sequence of memory address
6 8.1 Background ⚫ Memory address ⚫ Memory consist of a larger array of words or bytes, each with its own address ⚫ We do ignore how a program generates a memory address ⚫ We are interested only in the sequence of memory address