查询DAC0830供应商 March 2002 National Semiconductor DACO830/DAC0832 8-Bit uP Compatible Double-Buffered D to A Converters B General Description Features The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying Double-buffered, single-buffered or flow-through digital DAC designed to interface directly with the 8080, 8048 data inputs N 8085, Z80, and other popular microprocessors. A deposited a Easy interchange and pin-compatible with 12-bit silicon-chromium R-2R resistor ladder network divides the dac 1230 series eference current and provides the circuit with excellent Direct interface to all popular microprocessors temperature tracking characteristics(0.05% of Full Scale a Linearity specified with zero and full scale adjust Range maximum linearity error over temperature). The ci only-NOT BEST STRAIGHT LINE FIT. cuit uses CMos current switches and control logic to a Works with+10V reference-full 4-quadrant multiplication achieve low power consumption and low output leakage Can be used in the voltage switching mode current errors. Special circuitry provides TTL logic input volt- age level compatibility. a Logic inputs which meet TTL voltage level specs(1.4vo 彐 Double buffering allows these DACs to output a voltage corresponding to one digital word while holding the next a Operates "STAND ALONE (without uP)if desired digital word. This permits the simultaneous updating of any "Available in 20-pin small-outline or molded chip carrier number of DAcs The DAC0830 series are the 8-bit members of a family of Key specifications ocessor-compatible DACS( MICR ■ Resolution:8bits Linearity: 8, 9, or 10 bits (guaranteed over temp. 0002%FS/C Low power dissipation: 20 mW a Single power supply: 5 to 15 vpc Typical Application +VcC (+15 Voc) 1719182 00560801 BH-FET and MICRO-DAC are trademarks of National semiconductor Corporation. @2002 National Semiconductor Corporation DS005608 ww nation
DAC0830/DAC0832 8-Bit µP Compatible, Double-Buffered D to A Converters General Description The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the 8080, 8048, 8085, Z80®, and other popular microprocessors. A deposited silicon-chromium R-2R resistor ladder network divides the reference current and provides the circuit with excellent temperature tracking characteristics (0.05% of Full Scale Range maximum linearity error over temperature). The circuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors. Special circuitry provides TTL logic input voltage level compatibility. Double buffering allows these DACs to output a voltage corresponding to one digital word while holding the next digital word. This permits the simultaneous updating of any number of DACs. The DAC0830 series are the 8-bit members of a family of microprocessor-compatible DACs (MICRO-DAC™). Features n Double-buffered, single-buffered or flow-through digital data inputs n Easy interchange and pin-compatible with 12-bit DAC1230 series n Direct interface to all popular microprocessors n Linearity specified with zero and full scale adjust only — NOT BEST STRAIGHT LINE FIT. n Works with ±10V reference-full 4-quadrant multiplication n Can be used in the voltage switching mode n Logic inputs which meet TTL voltage level specs (1.4V logic threshold) n Operates “STAND ALONE” (without µP) if desired n Available in 20-pin small-outline or molded chip carrier package Key Specifications n Current settling time: 1 µs n Resolution: 8 bits n Linearity: 8, 9, or 10 bits (guaranteed over temp.) n Gain Tempco: 0.0002% FS/˚C n Low power dissipation: 20 mW n Single power supply: 5 to 15 VDC Typical Application 00560801 BI-FET™ and MICRO-DAC™ are trademarks of National Semiconductor Corporation. Z80® is a registered trademark of Zilog Corporation. March 2002 DAC0830/DAC0832 8-Bit µP Compatible, Double-Buffered D to A Converters © 2002 National Semiconductor Corporation DS005608 www.national.com 查询DAC0830供应商
I Connection Diagrams(Top Views Dual-In-Line and Small-Outline Packages LLE(BYTE1/BYTE2)t D 56021 Molded Chip Carrier Package WR2XFER DIA DIs DI6 LE(rE/E217161514 Dl7(MSB) ww.national. com
Connection Diagrams (Top Views) Dual-In-Line and Small-Outline Packages 00560821 Molded Chip Carrier Package 00560822 DAC0830/DAC0832 www.national.com 2
Absolute Maximum Ratings(Notes 1 Dual-In-Line Package(plastic) If Military/Aerospace specified devices are required, Surface Mount Package please contact the National Semiconductor Sales Office/ Vapor Phase(60 sec. 215C Supply Voltage (Vcc) Voltage at Any Digital Input Vec to gnD Operating Conditions Voltage at VRI 65cto+150°c Temperature Range T Storage Temperature Range Part numbers with "LCN suffix Package Dissipation 0°cto+70°C Part numbers with "LCWM" suffix 0cto+70°C at TA=25C(Note 3) 500mW Part numbers with "Lcv suffix 0°cto+70°C Part numbers with "LCJ" suffix lOuT or lOuT?(Note 4) 100 mV to Vcc 40°cto+85'c ESD Susceptability(Note 4) Part numbers with"LJ suffix -55cto+125°c 800v Lead Temperature( Soldering, 10 sec. Voltage at Any Digital Input Electrical Characteristics VREF=10000 Voc unless otherwise noted Boldface limits apply over temperature, TMINSTASTMAx For all other limits TA=25 C Vcc=5voc±5% Vo=4.75 V Vcc =15.75 voc ±5% Limit Parameter Conditions to15Voc±5% Tested Limit Limit (Note 12 CONVERTER CHARACTERISTICS Resolution Linearity Error Max Zero and full scale adjuste -10VSVREFS+10V DACo83oL LJ 0.05 FSR DACo832LJ LC FSR DACO830LCN. LCWM FSR DACO831LCN 0.1 % FSR DACO832LCN CWM 0.2 FSR LCV Differential Nonlinearity Zero and full scale adjusted Max 10v≌VRE≤+10V DACo830Lj& LC 0.1 FSR DACo832LJ& LCJ DACO830LCN. LCWM FSR DACO832LCN. LCWM 0.4 FSR 10v≌ VREF LJ&LcJ 8 ≤+10V LCN. LCWM Gain Error Max Using Internal Rb ±0.2 % FS Gain Error Tempco Max Using internal RIb 0.0002 0.0006 3
Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 17 VDC Voltage at Any Digital Input VCC to GND Voltage at VREF Input ±25V Storage Temperature Range −65˚C to +150˚C Package Dissipation at TA=25˚C (Note 3) 500 mW DC Voltage Applied to IOUT1 or IOUT2 (Note 4) −100 mV to VCC ESD Susceptability (Note 4) 800V Lead Temperature (Soldering, 10 sec.) Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) 300˚C Surface Mount Package Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C Operating Conditions Temperature Range TMIN≤TA≤TMAX Part numbers with “LCN” suffix 0˚C to +70˚C Part numbers with “LCWM” suffix 0˚C to +70˚C Part numbers with “LCV” suffix 0˚C to +70˚C Part numbers with “LCJ” suffix −40˚C to +85˚C Part numbers with “LJ” suffix −55˚C to +125˚C Voltage at Any Digital Input VCC to GND Electrical Characteristics VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits TA=25˚C. Parameter Conditions See Note VCC = 4.75 VDC VCC = 15.75 VDC VCC =5VDC ±5% VCC = 12 VDC ±5% to 15 VDC ±5% Limit Units Typ (Note 12) Tested Limit (Note 5) Design Limit (Note 6) CONVERTER CHARACTERISTICS Resolution 8 8 8 bits Linearity Error Max Zero and full scale adjusted 4, 8 −10V≤VREF≤+10V DAC0830LJ & LCJ 0.05 0.05 % FSR DAC0832LJ & LCJ 0.2 0.2 % FSR DAC0830LCN, LCWM & LCV 0.05 0.05 % FSR DAC0831LCN 0.1 0.1 % FSR DAC0832LCN, LCWM & LCV 0.2 0.2 % FSR Differential Nonlinearity Zero and full scale adjusted 4, 8 Max −10V≤VREF≤+10V DAC0830LJ & LCJ 0.1 0.1 % FSR DAC0832LJ & LCJ 0.4 0.4 % FSR DAC0830LCN, LCWM & LCV 0.1 0.1 % FSR DAC0831LCN 0.2 0.2 % FSR DAC0832LCN, LCWM & LCV 0.4 0.4 % FSR Monotonicity −10V≤VREF LJ & LCJ 4 8 8 bits ≤+10V LCN, LCWM & LCV 8 8 bits Gain Error Max Using Internal Rfb 7 ±0.2 ±1 ±1 % FS −10V≤VREF≤+10V Gain Error Tempco Max Using internal Rfb 0.0002 0.0006 % DAC0830/DAC0832 3 www.national.com
Electrical Characteristics(Continued) VREF=10000 Vpc unless otherwise noted Boldface limits apply over temperature, TMINSTASTMAx For all other limits s°o Vcc =4. VI Vcc =12 voc Vcc =15.75 vpc Note to15voc±5% Limit ( Note 12) (Note 5) ( Note 6 CONVERTER CHARACTERISTICS FS/C Power Supply Rejection All digital inputs latched high Vcc14. 5v to 15.5V 0.0002 0.0025 11.5vto12.5V 4.5to5.5V 0.013 0.015 Min 15 Output Feedthrough VREF=20 Vp-p, f=100 kHz All data inputs latched low OuT1 All data inputs LJ&LCJ 10 Leakage latched low LCN. LCWM Current Max DUT2 All data inpu lcJ latched high LCN, LCWM& 50 LCV All data inputs JT2 latched low 115 DIGITAL AND DC CHARACTERISTICS LJ:4.75V 0.6 07 LcJ:15.75v LCN. LCWM. LCV Min Logic Hig lj lcj 2.0 LCN. LCWM. LCV 19 2.0 Digital Input Max Digital inputs <0.8V l & lcj LCN. LCWM. LCV -200 LCN. LCWM. LCV upply Current Max L & lcj 1 ww. national co
Electrical Characteristics (Continued) VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits TA=25˚C. Parameter Conditions See Note VCC = 4.75 VDC VCC = 15.75 VDC VCC =5VDC ±5% VCC = 12 VDC ±5% to 15 VDC ±5% Limit Units Typ (Note 12) Tested Limit (Note 5) Design Limit (Note 6) CONVERTER CHARACTERISTICS FS/˚C Power Supply Rejection All digital inputs latched high VCC=14.5V to 15.5V 0.0002 0.0025 % 11.5V to 12.5V 0.0006 FSR/V 4.5V to 5.5V 0.013 0.015 Reference Max 15 20 20 kΩ Input Min 15 10 10 kΩ Output Feedthrough Error VREF=20 Vp-p, f=100 kHz All data inputs latched low 3 mVp-p Output Leakage Current Max IOUT1 All data inputs LJ & LCJ 10 100 100 nA latched low LCN, LCWM & LCV 50 100 IOUT2 All data inputs LJ & LCJ 100 100 nA latched high LCN, LCWM & LCV 50 100 Output IOUT1 All data inputs 45 pF Capacitance IOUT2 latched low 115 IOUT1 All data inputs 130 pF IOUT2 latched high 30 DIGITAL AND DC CHARACTERISTICS Digital Input Max Logic Low LJ: 4.75V 0.6 Voltages LJ: 15.75V 0.8 LCJ: 4.75V 0.7 VDC LCJ: 15.75V 0.8 LCN, LCWM, LCV 0.95 0.8 Min Logic High LJ & LCJ 2.0 2.0 VDC LCN, LCWM, LCV 1.9 2.0 Digital Input Max Digital inputs <0.8V Currents LJ & LCJ −50 −200 −200 µA LCN, LCWM, LCV −160 −200 µA Digital inputs>2.0V LJ & LCJ 0.1 +10 +10 µA LCN, LCWM, LCV +8 +10 Supply Current Max LJ & LCJ 1.2 3.5 3.5 mA Drain LCN, LCWM, LCV 1.7 2.0 DAC0830/DAC0832 www.national.com 4
Electrical Characteristics VREF=10000 Voc unless otherwise noted. Boldface limits apply over temperature, TMINSTASTMAX For all other lin T=25°C Vcc=15.75 Vpc Vpc+5% to 15 Vcc=4.75 V Vcc=5 VDc±5% Parameter Tested Design Limit TypTested (Note 12) (Note 5)(Note 6) AC CHARACTERISTICS 1.0 1.0 Write and XFER VI 00 375 600 Pulse Width Min 320 320 900 tps Data Setup Time VI=OV, 00 250 VIL=5V 320 900 Data Hold Time V=OV 50 VIL=5V tcs Control Setup Vu=ov 110 250 Time VI=5V 320 320 1100 CH Control Hold Time VI=OV. 0 0 VIH=5V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. with respect to GND, unless otherwise specified. allowable power dissipation at any temperature is Pp=(Jmax- TA)eJa or the number given in the Absolute Maximum Ratings, whichever is lowe nis de TJMAx =125.C (plastic) or 150C (ceramic), and the typical junction-to-ambient thermal resistance of the j package when board mounted is 80 ackage, this number increases to 100C/ and for the v package this number is 120"C/. Note 4: For current switching applications, both lOuT and louT must go to ground or the"Virtual Ground of an operational amplifier. The linearity emor is degraded by approximately Vos +VREF. For example, if VREF 10v then a 1 mv offset, Vos on lOuT or louT will introduce an additional 0.01% linearity error. Note 5: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level). Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels Note7: Guaranteed at VREF=±10 Vpc and vReF=±1vt Note 8: The unitFSR"stands for "Full Scale Range. ""Linearity Emor" and "Power Supply Rejection specs are based on this unit to eliminate dependence on a articular VREF value and to indicate the true performance of the part. The "Linea or specifica the DACO830 is 0.05% of FSR(MAX)". This guarantees that after performing a zero and full scale adjustment(see Sections 2.5 and 2.6). the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a straight line which passes through zero and full scale Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only. Note 10: A 100nA leakage current with R, =20k and VREF=10V corresponds to a zero error of(100x10-9x20x103 x100/10 which is 0.02%of FS Note 11: The entire write pulse must occur within the valid data interval for the specified tw, 'os, tDH and ts to apply Note 12: Typicals are at 25C and represent most likely parametric Note 13: Human body model, 100 pF discharged through a 1.5 k]2 resistor. 5
Electrical Characteristics VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits TA=25˚C. Symbol Parameter Conditions See Note VCC=15.75 VDC VCC=12 VDC±5% to 15 VDC ±5% VCC=4.75 VDC VCC=5 VDC±5% Limit Units Typ (Note 12) Tested Limit (Note 5) Design Limit (Note 6) Typ (Note 12) Tested Limit (Note 5) Design Limit (Note 6) AC CHARACTERISTICS ts Current Setting VIL=0V, VIH=5V 1.0 1.0 µs Time tW Write and XFER VIL=0V, VIH=5V 11 100 250 375 600 Pulse Width Min 9 320 320 900 900 tDS Data Setup Time VIL=0V, VIH=5V 9 100 250 375 600 Min 320 320 900 900 tDH Data Hold Time VIL=0V, VIH=5V 9 30 50 ns Min 30 50 tCS Control Setup Time VIL=0V, VIH=5V 9 110 250 600 900 Min 320 320 1100 1100 tCH Control Hold Time VIL=0V, VIH=5V 9 0 0 10 0 0 Min 0 0 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N package, this number increases to 100˚C/W and for the V package this number is 120˚C/W. Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error. Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 7: Guaranteed at VREF=±10 VDC and VREF=±1 VDC. Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a particular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a straight line which passes through zero and full scale. Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only. Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x10−9x20x103)x100/10 which is 0.02% of FS. Note 11: The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply. Note 12: Typicals are at 25˚C and represent most likely parametric norm. Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor. DAC0830/DAC0832 5 www.national.com