intersil CD4518BMS CD4520BMS December 1992 CMOS Dual Up counters Features Pinout High Voltage Ty pes(20V Rating) CD4518BMS, CD4520BMS CD4518BMS Dual BCD Up Counter TOP VIEW CD4520BMS Dual Binary Up Counter Medium Speed Operation 6MHz Typical Clock Frequency at 10V ENABLE A回 15RESETB Positive or Negative Edge Triggering 1A区 14Q4B Synchronous Internal Carry Propagation 13Q3B 100% Tested for Quiescent Current at 20V 12 5v, 10V and 15V Parametric Ratings 田QB Maximum Input Current of 1uA at 18V Over Full Pack RESET A区 回 ENABLE B age Temperature Range; 100nA at 18V and +25C 9CLOCKB Noise Margin(Over Full Package/ Temperature Range) 1V at VDD= 5V 2V at VDD= 10V 2.5V at VDD= 15V Standardized Symmetrical Output Characteristics Meets All Requirements of JEDEC Tentative Standard No. 13B,"Standard Specifications for Description of Functional Diagram 'B Series CMos Devices Applications Multistage Synchronous Counting Q1A CLOCK A ÷10:16 Multistage Ripple Counting Q2A Frequency Dividers Description RESET A CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going Q CLOCK B or negative-going transition. For single unit operation the 10÷1612 ENABLE input is maintained high and the counter advances ENABLE on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines The counter can be cascaded in the ripple mode by connect ing Q4 to the enable input of the subse equent counter while RESETB the CLOCK input of the latter is held low The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages Braze seal DIP H4S Frit Seal DIP Ceramic Flatpack *H6P tH6W CD4518B Only tCD4520B Only CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures ile Number 3342 1-888-INTERSIL or 321-724-71431 Copyright Intersil Corporation 1999 7-1206
7-1206 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 December 1992 CD4518BMS, CD4520BMS CMOS Dual Up Counters Features • High Voltage Types (20V Rating) • CD4518BMS Dual BCD Up Counter • CD4520BMS Dual Binary Up Counter • Medium Speed Operation - 6MHz Typical Clock Frequency at 10V • Positive or Negative Edge Triggering • Synchronous Internal Carry Propagation • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Multistage Synchronous Counting • Multistage Ripple Counting • Frequency Dividers Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4S Frit Seal DIP H1F Ceramic Flatpack *H6P †H6W *CD4518B Only †CD4520B Only File Number 3342 Pinout CD4518BMS, CD4520BMS TOP VIEW Functional Diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK A ENABLE A Q1A Q2A Q3A Q4A VSS RESET A VDD Q4B Q3B Q2B Q1B ENABLE B CLOCK B RESET B VSS = 8 VDD = 16 ÷10/÷16 C R 1 4 5 6 Q1A Q2A Q3A Q4A RESET A 7 2 CLOCK A ENABLE A ÷10/÷16 C R 9 12 13 14 Q1B Q2B Q3B Q4B RESET B 15 10 CLOCK B ENABLE B 3 11
Specifications CD4518BMS, CD4520BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD 0.5V to +20V Thermal Resistance (Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package 80°cM20°cM Input Voltage Range, All Inputs -0.5v to VDD +o5v Flatpack Package 70 CN 20CN DC Input Current, Any One Input #10ma Maximum Package Power Dissipation(PD)at+125C Operating Temperature Range -55cto+125° C For TA=-55°cto+100°c( Package Type D,F,K Package Types D, F, K, H For TA=+100°cto+125°c( Package Type D,F,K) Storage Temperature Range (TSTG) -65°Cto+150°c Linearity at 12mw/C to 200mW Lead Temperature(During Soldering) +265c Device Dissipation per Output Transistor At Distance 1/16+ 1/32 Inch(1.59mm t 0.79mm) from case for For TA= Full Package Temperature Range(All Package Types 10s Maximum Junction Temperature +175°C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD= 20V, VIN= VDD or GND +125°c VDD= 18V. ViN E VDD or gND AA Input Leakage Current lIL VIN=VDD or GND VDD=20 +25°C 100 +125°C 1000 VDD=18V -55°C 100 Input Leakage Current H VIN= VDD or GND VDD= 20 +25°C +125°C 1000 VDD=18V -55°C Output Voltage VOL15 VDD=15V, No Load 1,23|+25°C,+125°,55° 50 mV Output Voltage VOH15 VDD= 15V, No Load(Note 3) 1,2,3 25°C,+125°C,-55°C1495 Output Current (Sink) OL5 VDD= 5V, VOUT=0.4V +25°C 0.53 Output Current( Sink) IOL10 VDD= 10V, VOUT =0.5V +25°C Output Current (Sink) IOL15 VDD= 15V VOUT= 1.5V +25°C Output Current(Source) IOH5A VDD=5V, VOUT =4.6V +25°C Output Current(Source) IOH5B VDD= 5V, VOUT =2.5V +25°C AAAA Output Current(Source) IOH10 VDD= 10V, VOUT =9.5V +25°C Output Current(Source) IOH15 VDD= 15V, VOUT =13.5V 25°C -35mA N Threshold Voltage VNTH VDD=10V, ISS=-10uA +25°C 2807 P Threshold voltage VPTH VSS=OV, IDD= 10A +25°C 2.8|V F VDD=2.8V, VIN= VDD or GND +25°C VDD= 20V. vin a vdd or gnD +25°C VDD/2 VDD/2 7 VDD= 18V. ViN E VDD or gND VdD= 3V. vin a VdD or GND -55°C Input voltage LOw ⅦLMD=5V,VoH>45woL<051,2,3+25°c,+1259C,-55c Input voltage High HvDD=5VoH>45oL<051,2,3+25℃+125%0-5535V Input voltage LOw D=15V.VoH>13.5 1,23|+25°C,+125°,55° VoL≤15V Input voltage High ⅦHVDD=15V,vOH>13.5V 25°C,+125°C,-55°C11 OL<1.5V NOTES: 1. All VO referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD Limit is 0.050V max Go/No Go test with limits applied to inputs 7-1207
7-1207 Specifications CD4518BMS, CD4520BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . .Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE LIMITS MIN MAX UNITS Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VDD/2 VOL < VDD/2 V VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max
Specifications CD4518BMS, CD4520BMS TABLE 2 AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS(NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS VDD 5V Vin E Vdd or GND +25°C Clock to Output TPLH1 10,11 +125°c,-55°C Propagation Delay TPHL2 VDD= 5V VIN= VDD or GND +25°C Reset to Ouput 10.11 125°C.-55°C Transition Time TTHL VDD=5V, VIN= VDD or GND (Note 2) TTLH 10,11+125°C,-55°C Maximum Clock Input FCL VDD= 5V, VIN=VDD or GND Frequency 1011+1250.5011·Mz NOTES CL= 50pF, RL= 200K, Input TR, TF 20ns 2.-55C and +125C limits guaranteed, 100% testing being implemented TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD= 5V, ViN= VDD or GND 55°C.+25°C +125° 150 VDD= 10V viN= VDD or GND 1.2 55%c+25% VDD= 15V. ViN= DD or GND Output Voltage VOL VDD= 5V, No Load 1.2 +25°C,+125°C, Output Voltage VDD= 1 2 +25°.+125°C VOH VDD 1,2+25°0,+125°0,495 55° Output Voltage VOH VDD=10V, No Load 1.2 +25°C,+125°C,995 55° Output Current (Sink) OL5 VDD= 5V, VOUT=0.4V 1.2 55°c Output Current(Sink) OL10 VDD= 10V VOUT=0.5V 1.2 0 -55°C mA Output Current (Sink) OL15VDD= 15V, VOUT=1.5V +125°C 4.2 Output Current (Source) IOH5A VDD= 5V, VOUT= 4.6V +125°C -036mA -0.64 mA Output Current(Source) IOH5B VDD= 5V, VOUT=2.5V 1.2 +125° 115 55° Output Current(Source) IOH10 VDD= 10V, VOUT=9.5v 1.2 125°C -55°c mA Output Current(Source)I IOH15 VDD=15V, VOUT =13.5V 125° -4.2 mA I Input Voltage Low VIL VDD= 10V, VOH>9V, VOL< 1V 1.2 +25°C.+125°C Input Voltage High VIH VDD= 10V, VOH>9V. VOL 1V 1.2 +25°C,+125°C,+7 -55°C 7-1208
7-1208 Specifications CD4518BMS, CD4520BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE LIMITS MIN MAX UNITS Propagation Delay Clock to Output TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 560 ns 10, 11 +125oC, -55oC - 756 ns Propagation Delay Reset to Ouput TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 650 ns 10, 11 +125oC, -55oC - 878 ns Transition Time (Note 2) TTHL TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND 9 +25oC 1.5 - MHz 10, 11 +125oC, -55oC 1.11 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA +125oC - 150 µA VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA +125oC - 300 µA VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA +125oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA -55oC - -0.64 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA -55oC - -2.0 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA -55oC - -1.6 mA Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V
Specifications CD4518BMS, CD4520BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS(Continued) LIMITS PARAMETER SYMBOL TEMPERATURE MIN TPHL1 VDD= 10V 1,2,3 230 Clock to Output TPLH1 VDD= 15V 1,2,3 25°C opagation Delay TPHL2 VDD= 10V +25°C 225 VDD= 15V 1,2,3 +25°C Transition Time TTHL VDD= 10V 1,2,3 TTLH VDD=15V 1,2,3 +25°C aximum Clock Input 1,2,3 Frequency VDD= 15V 1.2.3 MHZ Maximum Clock Rise and TRCL VDD =5V 1,2,3 +25°C Fall Time TFCL 1.2.3.4 +25°C VDD= 15V 1.2.3 minimum Enable pulse TW VDD= 5V 1,2,3 25°C ns VDD= 15V 1,2,3 +25°C ns Minimum Reset Pulse W VDD= 5V 1,2,3 Width VDD= 10V +25°C 110 Minimum clock pulse W VDD 5V 1.2.3 Width 1.2.3 ns +25°C Input Capacitance CIN Any Input 1.2 25°C 1. All voltages referenced to device GND 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized n initial design release and upon design changes which would affect these characteristics. 3. CL= 50pF, RL 200K, Input TR, TF < 20ns 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL TEMPERATURE MAXUNITS Supply Current VDD= 20V ViN= VDD or GND N Threshold Voltage VNTH VDD= 10V, ISS=-10w 1.4 +25°C -28 -0.2 N Threshold Voltage △ TN VDD=10V,ss=10A 1.4 25°c Delta P Threshold Voltage VTP VSS=,IDD=10uA +25°C △ VTP VSS=0V,|DD=10uA +25°C VVVVV VDD= 18V. ViN= VDD or GND VOH> VOL< VDD= 3V. ViN= VDD or GND VDD/2 VDD/2 Propagation Delay Time TPHL VDD=5V 1,2,3,4 +25°C 1.35 ns TPLH +25°C NOTES: 1. All voltages referenced to device GND 2. CL= 50pF, RL= 200K, Input TR, TF 20ns 4. Read and record 7-1209
7-1209 Specifications CD4518BMS, CD4520BMS Propagation Delay Clock to Output TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 230 ns VDD = 15V 1, 2, 3 +25oC - 160 ns Propagation Delay Reset to Output TPHL2 VDD = 10V 1, 2, 3 +25oC - 225 ns VDD = 15V 1, 2, 3 +25oC - 170 ns Transition Time TTHL TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns Maximum Clock Input Frequency FCL VDD = 10V 1, 2, 3 +25oC 3 - MHz VDD = 15V 1, 2, 3 +25oC 4 - MHz Maximum Clock Rise and Fall Time TRCL TFCL VDD = 5V 1, 2, 3, 4 +25oC - 15 µs VDD = 10V 1, 2, 3, 4 +25oC -5 µs VDD = 15V 1, 2, 3, 4 +25oC -5 µs Minimum Enable Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 400 ns VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 140 ns Minimum Reset Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 250 ns VDD = 10V 1, 2, 3 +25oC - 110 ns VDD = 15V 1, 2, 3 +25oC - 80 ns Minimum Clock Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 70 ns Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS MIN MAX UNITS Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VDD/2 VOL < VDD/2 V VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS MIN MAX UNITS
Specifications CD4518BMS, CD4520BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C PARAMETER SYMBOL DELTA LIMIT Supply Current-MS1-2 ±1.0uA Output Current (Sink) 儿5±20% X Pre-Test Reading Output Current(Source) IOH5A=+ 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 CONFORMANCE GROUP GROUP A SUBGROUPS READ AND RECORD I Initial Test(Pre Burn-in) 100%5004 1.7.9 IDD. IOL5. 1OH5A Interim Test 1(Post Burn-In) 100%5 1,7,9 IDD. IOL5. IOH5A terim Test 2(Post Burn-In) 100%5004 1,7,9 DD. IOL5 IOH 5A PDA(Note 1) 100%5004 1.7.9. Deltas Interim Test 3( Post Burn-In) 100%5004 1,7,9 IDD. IOL5. 10H5A PDA(Note 1) 100%5004 1.7.9. Deltas Final Test 100%5004 2,3,8A,8B,10,11 Sample 5005 1,2,3,7,8A,8B,9,10,11 Group B Subgroup B-5 Sample500512378A8B,9,10,11Deas| Subgroups1,2,39,10.11 Subgroup B-6 Sample 5005 1,7,9 GroupD Subgroups 1, 23 NOTE: 1. 5% Parameteric 3% Functional: Cumulative for Static 1 and 2 TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRERRAD POST-RRAD PRE-RRAD POST-IRRAD Group E Subgroup 2 5005 1.7.9 Table 4 1.9 Table 4 TABLE 8 BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION GROUND ±5025H I Static Bum-In1 3-6.11-14 1,2,7-10,15 Note 1 Static Bum -In 2 3-6.11-14 8 1,2,7,9,10, Note 1 15.16 In Note 1 Irradiation 3-6,11-14 1,2,7,9,10, Note 2 15.16 NOTES: 1. Each pin ex 2. Each pin except VDD and GND will have a series resistor of 47K+ 5%: Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, 7-1210
7-1210 Specifications CD4518BMS, CD4520BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 5004 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6 Sample 5005 1, 7, 9 Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS MIL-STD-883 METHOD TEST READ AND RECORD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND VDD 9V ± -0.5V OSCILLATOR 50kHz 25kHz Static Burn-In 1 Note 1 3-6, 11-14 1, 2, 7-10, 15 16 Static Burn-In 2 Note 1 3-6, 11-14 8 1, 2, 7, 9, 10, 15, 16 Dynamic BurnIn Note 1 - 7, 8, 15 2, 10, 16 3-6, 11-14 1, 9 Irradiation Note 2 3-6, 11-14 8 1, 2, 7, 9, 10, 15, 16 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V