4、乘法运算控制器 ariel i MAX+plus lI-f: \dh\mp2 \eda tech_ app\e6_2 \sregab-larictl vhd - Text EditorI ES MAX+plus I Ele Edit Templates Assign Utilties Options Window Help 口圖舀△國囫郾巴郾四囚盈圖面剧函 Courier New」1B library ieee use ieee std logic 1164.alli use ieee std logic unsigned. all entity arictl is port(clk: in std logici start: in sto1。gic; ariend: out sta logici cikout:out std logici stall: out std logic)i end arictli architecture art of arictl is signal cnt4b: std logic vector (3 downto 0) ILine 11 Col 12INS 4
11 4、乘法运算控制器arictl
(haMAX+plus II-f:\dh\ mp2 (eda tech app\e6_2\sregab-farictlvhd-Text EditorI 回×」 3 MAX+pus Il Ele Edt Templates assign Utilities Options Window Hep 口圖舀属回△國囫国感国国為画武 Courier New.24B鐸鐸 begin stalks=start process(clk, start begin if start=l then cnt4<=0000i elsif clkf event and clk=f1 then if cnt4b<8 then cnt 4b<=cnt4b+l; end if: end if end processi LLine20col4|Ns←
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6)MAX+plus II-f:\dh(mp2\eda_tech_app\e6_2(sregab-[arictl vthd-Text Editor] FE MAX+plus I File Edit Templates Assign Utilities options Window Help 口厨舀帕△國原郾B感囚為圖蘭武雷 Courier New4已鐸圉 process(clk, cnt4b, start) begin if start=o then if cnt 4b<8 then clkout<=clk: ariend<=of else clkout<=o ariend<=li end if else clkout<=0i ariend<=ori end if; end process end arti Line 32[ Col 28 INS 4
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5、8位加法器 adder8b 8位加法器及4位加法程序见6.1节 49 MAX+plus II-h: \eda_ tech_ app\e6.1\adder8b_ 1- [adder8b_ 1. vhd- Text Editor] □x 或 Rs MAX+plus II Eile Edit Templates Assign Utilities Options window Help f」× 口回当属A△园码国盈回思雷oeN]2 library ieee use ieee std logic 1164. all; use leee std logic unsigned. all entity adder8b 1 i port(cin:in std logici a, b:in std logic vector(7 downto 0)i s: out std logic vector(7 downto 0)i cout: out stc1。gic) end adder 1: architecture art of adder8b 1 is signal sint: std logic vector(8 downto 0)i signal aa, bb: std logic vector(8 downto 0)i begin aa<=0’ sint<=aabb+cin s<=sint(7 downto 0); nt(8) end arti Line 10 Col 27 INS 4I
14 5、8位加法器adder8b 8位加法器及4位加法程序见6.1节。 或：