仿真结果: 6O MAX+plus II-h: \eda tech_app\e6 1\adder8b- [adder8b scf -aveform Ed ES MAX+plus II File Edit View Node Assign Utilities Options Window Help 口哆闆舀幽回△國囫卧感圖圖為圖匾副亟武會雷跟聞 L+Time: 1.47us Interval:1.47us Name 2000ns 4000ns hull s 800. 0ns US 4us D0010X20X3040X50X6070X80X%0100X110120X130X140 D00X20X40X60X80X100X120X140X160X180X200X220X240X4X24
6 仿真结果：
6.28位乘法器的设计 (MAX+plus II-h: \eda_ tech apple_1\adder8b-[multi8x8.gdf-Graphic Editor] S MAX+plus II Eile Edit View Symbol Assign Utilities Options Window Help 10 k R工cTL ARIE friend ADDER8B A3,, about[15.811 andsd70EA[7.o1 cou B[? SREG8B CLK LonD 0□ DIN【..。 REG16B Q【王s.o] UTPUT about(15.0 ands 7 ABIN IN[7
7 6.2 8位乘法器的设计
1、选通与门模块 andarith 19MAX+plus II-f:\dh\mp2\edatech_app\e62\andarith-Landarith, vhd- Text Editor ×」 FN MAX+plus ll Eile Edit Templates Assign lties Options window Hep librar leer use ieee std logic 1164.all entity andarith is port(abin: in std logic din: in std logic vector(/ downto 0) dout: out std logic vector(7 downto 0) end andarithi architecture art of andarith is begin process(abin, din) begin for i in o to 7 loop dout (i<=din(i) and abin end loop end process end arti Line 1 Col 1INS 4
8 1、选通与门模块andarith
2、16位锁存器regl6b MAX+plus II-f: \ dh\mp2 \eda tech_ app \e6_2\andarith-reg16b whd-Text EditorI R MAX+plus I Ele Edt Templates Assign Utilties options window Help ×」 library ieee; use ieee std logic 1164.all entity regl6b is port(clk, clr: in std logic d: in std logic vector(8 downto o) g: out std logic vector (15 downto 0))i end regl6bi rchitecture art of regl6b is signal rls: std logic vector (15 downto 0)i begi process(clk, clr) egl ifc1r=!1 then r16s<="0000000000000000"; elsif clkfevent and clk=1 then r16s(6 downto o<=r16s(7 downto 1) r16s(15 downto 7)<=d; end ifi end process a=r16s end art I Line 1[ Col 16 INSI
9 2、16位锁存器reg16b
3、8位右移寄存器sreg8b C,oMAX+plus II-f:dh\mp2 \eda tech_ app \e6 2\sregab-Isregab, vhd- Text EditorI N MAX+plus I Ele Edit Templates Assign Unities optons window Help library ieee use ieee std logic 64,a11 entity sreg8b is port(clk, load: in std logici din: in std logic vector (7 downto 0)i gb: out std logic)i end sreg8bi architecture art of sreg8b is signal reg8: std logic vector (7 downto 0)i begin process(clk, load begin if load=1 then reg<=dini elsif clkfevent and clk=1 then reg8(6 downto 0)<-reg8(7 downto 1)i end if end processi gb<=reg(o)i end arti ILine 13 Col 25 INS 41
10 3、8位右移寄存器sreg8b