intel. 8253/8253-5 PROGRAMMABLE INTERVAL TIMER MCS-85TM Compatible 8253-5 3 Independent 16-Bit Counters ■DCto2.6MH ■Available in EXPRESS Programmable Counter Modes Extended Tempraturnge I9hces5868Ma8eyT2aongef5epgenegpcge24pmpseOmperpepher &pe98g2838g8sr9smS1counles6aohwnha6eounaieodpo26M收Aumoeeod -GATEO CLK 1 ATE OUT 8253 GATE GNO 12 13DOUT -OUT 2 231306-2 NTERNAL BUS 231306- Figure 1.Block Diagram 3-51 rder m
intel 8253/8253-5 FUNCTIONAL DESCRIPTION RD(Read) A"low"on this input informs the 8253 that the CPU General is inputting data in the form of a counters value. w丽(Write) form of loading counters The 8253 solves one of the most common proble A0,A1 These inputs are normally connected to the address one of the counters of the 8253 bus. The r function is to select one of the three coun desired q anity.then upon tor mode selection. aooress the contr ent ot CS(Chip Select) priority levels. A "low"on this input enables the 8253.No reading Other counter/timer functions that are non-delay in the device s selecte tion of the counters. Programmable Rate Generator 。Event Counter .Binary Rate Multiplier ·Real Time Clock -GATE ·Digital One-Sho .Complex Motor Controller Data Bus Buffer tions.The Data Bus MODES of the 8253 3.Reading the count values. Read/Write Logic The Read/Write Logic accepts inputs from the sys. INTERNALUS ous and in turn 231306-3 tem edordisabled by 298a8oem2o8h8 Figure 3.Bl ck Diagram ving Data Bus /Write Logic F ction 3-52
intel 8253/8253-5 CSDW丽A1A0 010 oo Load Counter No o register for MODE programming. 0 1 001 Load Counter No.1 0 Load Counter No.2 Basically.the select inputs A0.A1 connect to the Write Mode Word 0o 10I 0 Read Counter No.0 ear select method.Or it can be conr 00 10 1 Read Counter No 1 0 0 11 0 Read Counter No 2 Sy%RoAngtadocode,sUchasaninai92o5orlarg8 0011 No-Operation 3-State x Disable 3-State 11 xX No-Operation 3-State Control Word Register A0.A soesrcoaregsterTheainto TE ction of binary or BCD counting OUT 1 33 o rea s contents is available CLK Z GATE Counter #0,Counter #1,Counter #2 nsists of a single.16-bit,pre-settable can outp 231306-4 Block Diagram Showing Control Word Hegister anc eration,binary or BCD.AIS o.there are special te ADDRESS AUS1 thees in th contr vare overne can be minimized for these functions. ds and lo can be read"on 8253 SYSTEM INTERFACE Rmgeomggnera6 The 231306-5 Figure 5.8253 System Interface 3.53
intel 8253/8253-5 OPERATIONAL DESCRIPTION RL-READ/LOAD: RL1 RLO General 0 I Counter Latching operation (see READ/WRITE Procedure Section). The complete functional definition of the 8253 10 Read/Load most significant byte only 01 each counter Read/Load least significant byte only. MODE 1 1 then most si ficant byte first, vte d.The se control words program the M M-MODE M2 M1 MO 0 0 Mode 0 ual counting 0 0 Mode 1 ona logic is pro on-chip som g and mproblems 0 Mode 2 ent of exte Mode3 o the microcom 0 0 Mode 4 0 Mode5 Programming the 8253 BCD: Binary Counter 16-Bits Binary Coded Decimal(BCD)Counter (4 Decades Counter Loading Control Word Format The D7 D6 D5 D4 D3 D2 D1 Do selected by the RL SC1 SCO RL1 RLO M2M1 MO BCD its).follow ed by a rising edge rior to that aling may yield invalid data. Definition Of Control MODE DEFINITION SC-SELECT COUNTER: MODE 0:Interrupt on Terminal Count.The outpu SC1 sco will be in after th mode set oper 0 0 Select Counter o 0 Select Counter 1 en terminal count is reac hed.theo 0 Select Counter 2 edwith the mode or a new count is load The eaaandecrementaherterl 3-54
intel. 8253/8253-5 In Modes 2 and 3.if a CLK source other than the gate input. e.After the the succeeding trig the gate input. unt after any rising edge of count will be inhibited while the GATE input is low. MODE 5:Hardware Trigs red Strobe.The counter nting after the rising edge of the trigge the next eq rminal count is reached.The counter is retn the count register is reloaded betwe not go low until the full count Signal Status Or Goino Rising High 3 Modes Low Thus.the gate input can be 0 Disables counting 1 1)Initiates then can aiso be synchronized by software counting 2) sets outpu one ha count been con 1)Disables 1)Reloads Enables This isa om ished by decrementing the 2)Set ounte counting k pulse.Whe nged and the counter high nt and the whole process is repeated. 3 1)Disables 1)Reloads Enables if the count is odd and the output is high,the firs 2)Sets unt by 1.Su uent clock uls imm high the ck by 2. the output goes lov 4 Disab Enables counting lock pu decrement the count b Initiates this way.if the count is odd,the ou put will be hia counting or (N 1)/2 counts and low for (N-1)/2 counts Flgure 6.Gate Pin Opera ations 3-55