FAIRCHILD January 2000 FM27C040 4,194,304-Bit(512K x 8)High Performance CMOS EPROM General Description Features organized FM27C0404194.304-Bit(512KX8)HUh mal read operation ■Ma ■JEDEC star sed systems exter -32-pin CERDI Performance Am62ZeernyeduengFarehtsarancedcwos Note:New revisic ets 70ns.Please check with factory for availability. Block Diagram 8+ e CMOS EPROM CE/POM a Y Gating C x Decoder 3-1 AMGTM is a trademark of WSI.Inc. o19eFairchidSemionductorCorporaion
1 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM General Description The FM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 512K words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The “Don’t Care” feature on VPP during read operations allows memory expansions from 1M to 8 Mbits with no printed circuit board changes. The FM27C040 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 120ns access time provides high speed operation with high-performance CPUs. The FM27C040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The FM27C040 is manufactured using Fairchild’s advanced CMOS AMG™ EPROM technology. Block Diagram January 2000 Features ■ High performance CMOS —120, 150ns access time* ■ Simplified upgrade path —VPP is a “Don’t Care” during normal read operation ■ Manufacturer’s identification code ■ JEDEC standard pin configuration —32-pin PDIP —32-pin PLCC —32-pin CERDIP DS800033-1 AMG™ is a trademark of WSI, Inc. © 1999 Fairchild Semiconductor Corporation Output Enable, Chip Enable, and Program Logic Y Decoder X Decoder . . . . . . . . . Output Buffers Y Gating 4,194,304-Bit Cell Matrix Data Outputs O0 - O7 VCC GND VPP OE CE/PGM A0 - A18 Address Inputs *Note: New revision meets 70ns. Please check with factory for availability
Connection Diagrams 27c010 FM27C040 27c010 复订第2第万苏器42200传67 FM27C040 4,194,304-Bit(512K x 8)High Pert Compatible EPROM pin are sho the blocks adjac tto the FM27C040 pin. Commercial Temperature Range Extended Temperature Range form (0℃to+70C)Vcc=5V±10% (-40°℃to+85C)Vcc=5V±10% Parameter/Order Number Access Time(ns) Parameter/Order Number Access Time(ns) FM27C0400NV90 90 EM27C040 OF NE VE 90 90 FM27C040Q.N,V120 120 FM27C040 QE,NE,VE 120 120 CMOS FM27C040Q.N,V150 150 FM27C040 QE,NE,VE 150 15o All versions are guaranteed to function for slower speeds. Package Types:FM27C040Q.N.V XXX =Quartz-Windowed Ceramic DIP EPROM Pin Names A0-A18 N=Plastic DIP Addresses V=PLCO CE/PGM Chip Enable/Program All to the JEDECstandard. Output Enable 00-07 Outputs XX Don't Care (During Read) FM27C040 Rev.A
2 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Connection Diagrams Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin. Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10% Parameter/Order Number Access Time (ns) FM27C040 Q, N, V 90 90 FM27C040 Q, N, V 120 120 FM27C040 Q, N, V 150 150 Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10% Parameter/Order Number Access Time (ns) FM27C040 QE, NE, VE 90 90 FM27C040 QE, NE, VE 120 120 FM27C040 QE, NE, VE 150 150 Package Types: FM27C040 Q, N,V XXX Q = Quartz-Windowed Ceramic DIP N = Plastic DIP V = PLCC • All packages conform to the JEDEC standard. • All versions are guaranteed to function for slower speeds. Pin Names A0–A18 Addresses CE/PGM Chip Enable/Program OE Output Enable O0–O7 Outputs XX Don’t Care (During Read) DS800033-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 XX/VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 27C010 XX/VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND FM27C040 27C010 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 VCC XX/PGM NC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
Absolute Maximum Ratings(Note 1) uore0a628o Vec +1.0V to GND-0.6V Storace temoerature -65℃t0+150℃ Operating Range FM27C040 -0.6Vto+7V Range Temperature Tolerance Va and A9 with Respect to Ground 0.6Vto+14 Vcc Commercial 0C to +70C +5V ±10% 4.194 -0.6Vto+7V 40Cto+85℃ +5V 士10% ESD Protection >2000V Read Operation DC Electrical Characteristics Over operating range with VP=Vcc 1-Bit(512K Symbol Parameter Test Conditions Min Max Units V Input Low Level 05 0 Vi Input High Level 2.0 cc+1 x 8)High V Output Low Voltage 1=2.1mA 0.4 Output High Voltage 6=2.5mA 35 81 Vcc Standby Current (CMOS) CE=Vcc±0.3V 100 A Performa Ve Standby Current CE=V mA VActive Current F-5 MHZ 的 mA la Vee Supply Current Vee Vcc 10 UA Vp Read Voltage Vcc-0.4 /cc u Input Load Current =5.5V or GND ho Output Leakage Current Vour=5.5V or GND 10 HA AC Electrical Characteristics Over operating range with Vep=Vco SymboI Parameter 120 150 Units Min Max Min Address to Output Delay 120 150 CE to Output Delay 120 150 Eto Output Delay 50 50 (Note 2) upu 6 55 ns Capacitance T=+25C.f=1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units Output Capacitance VOUT =OV 12 15 pF FM27C040 Rev.A
3 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Absolute Maximum Ratings (Note 1) Storage Temperature -65°C to +150°C All Input Voltages except A9 with Respect to Ground -0.6V to +7V VPP and A9 with Respect to Ground -0.6V to +14V VCC Supply Voltage with Respect to Ground -0.6V to +7V ESD Protection >2000V All Output Voltages with Respect to Ground VCC +1.0V to GND - 0.6V Operating Range Range Temperature VCC Tolerance Commercial 0°C to +70°C +5V ±10% Industrial -40°C to +85°C +5V ±10% Read Operation DC Electrical Characteristics Over operating range with VPP = VCC Symbol Parameter Test Conditions Min Max Units VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 VCC +1 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = -2.5 mA 3.5 V ISB1 VCC Standby Current (CMOS) CE = VCC ± 0.3V 100 µA ISB2 VCC Standby Current CE = VIH 1 mA ICC VCC Active Current CE = OE = VIL, f=5 MHz 30 mA I/O = 0 mA IPP VPP Supply Current VPP = VCC 10 µA VPP VPP Read Voltage VCC - 0.4 VCC V ILI Input Load Current VIN = 5.5V or GND -1 1 µA ILO Output Leakage Current VOUT = 5.5V or GND -10 10 µA AC Electrical Characteristics Over operating range with VPP = VCC Symbol Parameter 120 150 Units Min Max Min Max tACC Address to Output Delay 120 150 tCE CE to Output Delay 120 150 tOE OE to Output Delay 50 50 tDF Output Disable to 45 55 ns (Note 2) Output Float tOH Output Hold from Addresses CE or OE , 0 0 (Note 2) Whichever Occurred First Capacitance TA = +25°C, f = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance VIN = 0V 9 15 pF COUT Output Capacitance VOUT = 0V 12 15 pF
AC Test Conditions Output Load 1 TTL Gate and C =100 pF (Note 8) Input Rise and Fall Times <5 0s Input Pulse Levels 0.45Vto2.4W Timing Measurement Reference Level (Note 10) AC Waveforms(Notes 6,7.9) ADDRESSES V☐ Addresses Valid 6E6 FM27C040 4,194,304-Bit(512K x 8)High Performa OE DV QUTPUT al Ouput 2 D380003-4 CMOS sampegadsm10O%esteg EPROM d 6 a0.1F sed on every devics latch-up and g FM27C040 Rev.A
4 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM AC Test Conditions Output Load 1 TTL Gate and CL = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level (Note 10) Inputs 0.8V and 2V Outputs` 0.8V and 2V AC Waveforms (Notes 6, 7, 9) Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max. Addresses Valid Valid Output Hi-Z 2V 0.8V 2V 0.8V 2V 0.8V ADDRESSES OUTPUT CE OE tCE 2V 0.8V (Note 3) (Note 3) tDF (Note 4, 5) (Note 4, 5) tOH Hi-Z tOE tACC tCF DS800033-4
Programming Waveform(Note 13) ADORESSES DATA OH FM27C040 4,194,304-Bit(512K x 8)High D8300035 Programming Characteristics(Notes 11,12,13,14) Symbol Parameter Conditions Min Typ Max Units Performa Address Setup Time μs nce toes OE Setup Time us Data Setup Time V Setup Time Vcc Setup Time tAH Address Hold Time 0 Data Hold Time Ouput Enable to Output Float Delay CE/PGM=X 60 ns tow Program Pulse Width 50 10 Data Valid from CE/PGM=X 100 ns CE/PGM=Vi mA Vec Supply Current 30 mA Temn rature Amben 25 Vcc Power Supply Voltage 6.25 65 Vee Programming Supply Voltage 12.5 12.75 13.0 Input Rise.Fall Time ns Input Low Voitage 0.0 0.45 Input High Voltage 2.4 4.0 Input Timing Reference Voltage 0.8 2.0 Output Timing Reference Voltage 0.8 2.0 ot from twith or belore power is applied to V 5 FM27C040 Rev.A
5 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Programming Waveform (Note 13) Programming Characteristics (Notes 11, 12, 13, 14) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs tOES OE Setup Time 1 µs tDS Data Setup Time 1 µs tVPS VPP Setup Time 1 µs tVCS VCC Setup Time 1 µs tAH Address Hold Time 0 µs tDH Data Hold Time 1 µs tDF Output Enable to Output Float Delay CE/PGM = X 0 60 ns tPW Program Pulse Width 45 50 105 µs tOE Data Valid from OE CE/PGM = X 100 ns IPP VPP Supply Current during CE/PGM = VIL 30 mA Programming Pulse ICC VCC Supply Current 30 mA TA Temperature Ambient 20 25 30 °C VCC Power Supply Voltage 6.25 6.5 6.75 V VPP Programming Supply Voltage 12.5 12.75 13.0 V tFR Input Rise, Fall Time 5 ns VIL Input Low Voltage -0.1 0.0 0.45 V VIH Input High Voltage 2.4 4.0 V tIN Input Timing Reference Voltage 0.8 2.0 V tOUT Output Timing Reference Voltage 0.8 2.0 V Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: During power up the CE/PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP. tAS tAH Program Program Verify Address N tDF Data Out Valid ADD N Data In Stable ADD N Hi-Z tDS tDH t VCS tVPS tPW t OES tOE 2V 0.8V 2V 0.8V 6.25V 12.75V 2V 0.8V 2V 0.8V ADDRESSES DATA VPP CE/PGM OE VCC DS800033-5