W25Q64BVwinbond10.FUNCTIONALDESCRIPTION10.1SPIOPERATIONS10.1.1StandardSPIInstructionsTheW25Q64BVisaccessedthroughanSPlcompatiblebusconsistingoffoursignals:SerialClock(CLK),ChipSelect(ICS),SerialDataInput(DI)andSerialDataOutput(DO).StandardSPIinstructionsuse the Dl input pin to seriallywrite instructions,addresses or data to the device on the rising edge ofCLK.The DO output pin is used to read data or status from the device on the falling edge CLK.SPIbusoperationModes0(0.0)and3(1,1)aresupported.TheprimarydifferencebetweenMode0andMode3concernsthenormal stateof theCLK signal whentheSPIbusmasteris instandbyanddata isnotbeingtransferredtotheSerial Flash.ForModeOtheCLKsignal isnormallylowonthefallingandrising edges of/CS.For Mode3the CLK signal is normally highon the falling andrising edges of/CS.10.1.2DualSPIInstructionsTheW25Q64BVsupportsDualSPIoperationwhenusingthe“FastReadDualOutputandDualI/O"(3BandBBhex)instructions.Theseinstructionsallowdatatobetransferredtoorfromthedeviceattwotothreetimes the rate of ordinary Serial Flashdevices.TheDual Read instructions are ideal forquicklydownloading code to RAM upon power-up (code-shadowing)or for executing non-speed-critical codedirectly from the SPI bus (XiP). When using Dual SPI instructions the DI and DO pins becomebidirectional VO pins:100 and 101.10.1.3QuadSPlInstructionsTheW25Q64BVsupportsQuadSPloperationwhenusingthe"FastReadQuadOutput","FastReadQuadI/O"and"OctalWordReadQuad V/O"(6B,EBandE3hexrespectively).These instructions allowdatatobetransferredtoorfromthedevicefourto sixtimestherateof ordinarySerial Flash.TheQuadRead instructions offer a significant improvement in continuous and randomaccess transfer ratesallowingfastcode-shadowingtoRAMorexecutiondirectlyfromtheSPIbus(XiP).WhenusingQuadSPinstructionstheDIandDOpinsbecomebidirectionalIOoandIO1,andtheWPand/HOLDpinsbecomeIO2andIO3 respectively.QuadSPI instructionsrequirethenon-volatileQuad Enablebit (QE)inStatusRegister-2tobe set.10.1.4 HoldFunctionThe/HOLDsignalallowstheW25Q64BVoperationtobepausedwhileitisactivelyselected(when/CSislow).The/HOLDfunctionmaybeusefulincaseswheretheSPIdataandclocksignalsaresharedwithotherdevices.Forexample,consider ifthepagebufferwasonlypartiallywrittenwhenapriorityinterruptrequiresuseoftheSPIbus.Inthiscasethe/HOLDfunctioncansavethestateoftheinstructionandthedata in the buffer so programming can resume where it left off once the bus is available again. The/HOLDfunctionisonlyavailableforstandardSPIandDualSPIoperation,notduringQuadSPl.Toinitiatea/HOLDcondition,thedevicemustbeselectedwithICSlow.A/HOLDconditionwill activateonthefallingedgeof the/HOLDsignal if theCLKsignal isalreadylow.IftheCLKisnotalreadylowthe/HOLDconditionwill activateafterthenextfallingedgeofCLK.The/HOLDconditionwillterminateontherisingedgeof the/HOLDsignal if theCLKsignal isalreadylow.IftheCLKisnotalreadylowthe/HOLDcondition will terminateafterthenextfallingedgeof CLK.During a /HOLDcondition,theSerial DataOutput(DO)ishighimpedance,andSerialDataInput(DI)andSerialClock(CLK)areignored.TheChipSelect(/CS)signal shouldbekeptactive(low)forthefull durationofthe/HOLDoperationtoavoidresettingtheinternal logicstateofthedevicePublicationReleaseDate:July08.2010-11 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 11 - Revision E 10.FUNCTIONAL DESCRIPTION 10.1 SPI OPERATIONS 10.1.1 Standard SPI Instructions The W25Q64BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of /CS. 10.1.2 Dual SPI Instructions The W25Q64BV supports Dual SPI operation when using the “Fast Read Dual Output and Dual I/O” (3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become bidirectional I/O pins: IO0 and IO1. 10.1.3 Quad SPI Instructions The W25Q64BV supports Quad SPI operation when using the “Fast Read Quad Output”, “Fast Read Quad I/O” and “Octal Word Read Quad I/O” (6B, EB and E3 hex respectively). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 10.1.4 Hold Function The /HOLD signal allows the W25Q64BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device
W25Q64BVwinbond10.2WRITEPROTECTIONApplicationsthatusenon-volatilememorymusttakeinto considerationthepossibilityofnoiseandotheradversesystemconditionsthatmaycompromisedataintegrity.ToaddressthisconcerntheW25Q64Bvprovidesseveralmeanstoprotectdatafrominadvertentwrites10.2.1WriteProtectFeaturesDeviceresetswhenVcCisbelowthresholdTimedelaywritedisableafterPower-upWriteenable/disable instructionsandautomaticwritedisableafterprogramand eraseSoftwareandHardware(WPpin)writeprotection using Status RegisterWriteProtectionusingPower-downinstructionLock Down writeprotectionuntilnext power-up(1One Time Program (OTP) write protection(1)Note1:Thesefeaturesareavailableuponspecialorder.PleasecontactWinbondfordetails.Uponpower-uporatpower-down,theW25Q64BVwillmaintainaresetconditionwhileVCCisbelowthethreshold valueof Vw,(See Power-up Timing andVoltageLevels andFigure 31).Whilereset,alloperations aredisabledand no instructions arerecognized.During power-up and aftertheVCCvoltageexceeds Vw, all program and erase related instructions are further disabled for a time delay of tpuw. ThisincludestheWriteEnable.PageProgram,SectorErase,BlockErase.ChipEraseandtheWriteStatusRegisterinstructions.Notethatthechipselectpin(/CS)musttracktheVCCsupplylevelatpower-upuntiltheVCC-minlevelandtvsLtimedelayisreached.Ifneededapull-upresisteronICScanbeusedtoaccomplishthis.Afterpower-upthedeviceisautomaticallyplacedinawrite-disabledstatewiththeStatusRegisterWriteEnableLatch(WEL)settoaO.AWriteEnableinstructionmustbeissuedbeforeaPageProgram,SectorErase,Chip EraseorWriteStatus Registerinstruction willbeaccepted.After completingaprogram,eraseorwriteinstructiontheWriteEnableLatch(WEL)isautomaticallyclearedtoawrite-disabledstateof o.Software controlled write protection is facilitated using the Write Status Register instruction and settingtheStatusRegisterProtect(SRPo,SRP1)andBlockProtect(SEC,TB,BP2,BP1andBPO)bits.Thesesettingsallowaportionorallofthememorytobeconfiguredasreadonly.UsedinconjunctionwiththeWrite Protect (WP)pin,changes to the Status Register can be enabled or disabled under hardwarecontrol.SeeStatusRegisterforfurtherinformation.Additionally,thePower-downinstructionoffers anextra level of write protection as all instructions are ignored except for the Release Power-downinstruction.- 12
W25Q64BV - 12 - 10.2 WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the W25Q64BV provides several means to protect data from inadvertent writes. 10.2.1 Write Protect Features • Device resets when VCC is below threshold • Time delay write disable after Power-up • Write enable/disable instructions and automatic write disable after program and erase • Software and Hardware (/WP pin) write protection using Status Register • Write Protection using Power-down instruction • Lock Down write protection until next power-up(1) • One Time Program (OTP) write protection(1) Note 1: These features are available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q64BV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 31). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction
W25064BVwinbond11.CONTROLANDSTATUSREGISTERSThe Read Status Register-1 andStatus Register-2instructions canbe used toprovidestatus on theavailability of theFlash memory array,if the device iswrite enabled or disabled,thestateof writeprotection and theQuadSPI setting.The WriteStatusRegister instructioncanbe usedto configurethedeviceswriteprotectionfeaturesandQuadSPIsetting.WriteaccesstotheStatusRegisteriscontrolledbythestateofthenon-volatileStatusRegisterProtectbits(SRPo,SRP1),theWriteEnableinstruction,andinsomecasestheWPpin.11.1STATUSREGISTER11.1.1BUSYBUsY is a read only bit in the status register (So)that is set to a 1 state when the device is executing aPageProgram,Sector Erase,Block Erase,Chip Eraseor Write Status Register instruction.During thistimethedevicewill ignorefurtherinstructionsexceptfortheReadStatus RegisterandEraseSuspendinstruction(seetw,tpp,tsE,tBE,andtcEinACCharacteristics).Whentheprogram,eraseorwritestatusregisterinstructionhas completed,the BUsYbit willbeclearedtoa O state indicatingthedevice isreadyforfurtherinstructions.11.1.2 Write Enable Latch (WEL)Write Enable Latch (WEL) is a read only bit in the status register (S1)that is set to a 1 after executing aWriteEnableInstruction.TheWELstatusbit isclearedtoaOwhenthedeviceiswritedisabled.Awritedisable state occurs upon power-up or after any of the following instructions:Write Disable,PageProgram,SectorErase,BlockErase,ChipEraseandWriteStatusRegister.11.1.3BlockProtectBits(BP2,BP1,BP0)The Block Protect Bits (BP2, BP1, BPO)are non-volatile read/write bits in the status register (S4, S3,andS2)thatprovideWriteProtectioncontrolandstatus.BlockProtectbitscanbesetusingtheWriteStatusRegister Instruction(see twinAC characteristics).All,none oraportionof the memoryarray canbeprotected fromProgramandErase instructions(seeStatusRegisterMemoryProtectiontable).ThefactorydefaultsettingfortheBlockProtectionBits iso,noneofthearrayprotected.11.1.4 Top/Bottom Block Protect(TB)Thenon-volatileTop/Bottombit(TB)controlsiftheBlockProtectBits(BP2,BP1,BPo)protectfromtheTop(TB=O)ortheBottom(TB=1)ofthearrayasshownintheStatusRegisterMemoryProtectiontable.The factorydefault setting is TB=0.The TB bit canbe set with theWriteStatus Register InstructiondependingonthestateoftheSRPO,SRP1andWELbits.11.1.5Sector/BlockProtect(SEC)Thenon-volatileSectorprotectbit(SEC)controlsiftheBlockProtectBits(BP2,BP1,BPO)protect4KBSectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shownintheStatusRegisterMemoryProtectiontable.ThedefaultsettingisSEC=0.Publication Release Date:July 08.2010- 13 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 13 - Revision E 11. CONTROL AND STATUS REGISTERS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and in some cases the /WP pin. 11.1 STATUS REGISTER 11.1.1 BUSY BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. 11.1.2 Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register. 11.1.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. 11.1.4 Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. 11.1.5 Sector/Block Protect (SEC) The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0
W25Q64BVwinbond11.1.6 StatusRegisterProtect (SRP1, SRP0)TheStatusRegisterProtectbits(SRP1andSRPo)arenon-volatileread/writebitsinthestatusregister(S8 and S7).The SRPbits control the method of write protection:software protection,hardwareprotection,powersupplylock-downoronetimeprogrammable(OTP)protection.StatusSRP1SRPOWPDescriptionRegisterSoftwareWPpinhasnocontrol.TheStatusregistercanbewrittento00XProtectionafteraWriteEnableinstruction,WEL=1.[FactoryDefault]HardwareWhenWPpinislowtheStatusRegisterlockedandcannot00Protectedbewrittento.HardwareWhenWPpinishightheStatusregisterisunlockedandcan01UnprotectedbewrittentoafteraWriteEnableinstruction,WEL=1PowerSupplyStatus Register is protected and can not bewritten to again0X7until thenextpower-down,power-up cycle.(2)Lock-Down(1)OneTimeStatusRegisterispermanentlyprotectedandcannotbe1XProgram()written to.Note:1.Thesefeaturesareavailableuponspecialorder.PleasecontactWinbondfordetails2.When SRP1,SRPO=(1,0),apower-down,power-upcyclewill change SRP1,SRPOto (0,0)state.11.1.7QuadEnable(QE)TheQuadEnable(QE)bitisanon-volatileread/writebitinthestatusregister(S9)thatallowsQuadoperation.When theQEbit is set to a O state (factorydefault)theWPpin and/Hold areenabled.WhentheQEbitissettoa1theQuadIO2andIO3pinsareenabled.WARNING:TheQEbitshouldneverbesettoa1duringstandardSPIorDualSPIoperationif theWPor/HOLDpinsaretieddirectlytothepowersupplyorground.-14
W25Q64BV - 14 - 11.1.6 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down(1) Status Register is protected and can not be written to again until the next power-down, power-up cycle.(2) 1 1 X One Time Program(1) Status Register is permanently protected and can not be written to. Note: 1. These features are available upon special order. Please contact Winbond for details. 2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 11.1.7 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When the QE bit is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground
W25Q64BVwinbondS756S5S45352SS0TBBP1SRPOSECBP2BPOWELBUSYSTATUS REGISTER PROTECT O(NON-VOLITILE)SECTORPROTECT(NON-VOLITILE)TOP/BOTTOMWRITEPROTECT(NON-VOLITILE)BLOCKPROTECTBITS(NON-VOLITILE)WRITE ENABLE LATCHERASEORWRITEINPROGRESSFigure 3a. Status Register-1S15S14S12S1058S13S11S9(R)(R)(R)(R)QESRP1(R)RESERVEDQUADENABLE(NON-VOLITILE)STATUS REGISTER PROTECT 1(NON-VOLITILE)Figure 3b.Status Register-2PublicationReleaseDate:July08.2010- 15 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 15 - Revision E Figure 3a. Status Register-1 Figure 3b. Status Register-2