W25Q64BVwinbond3.PINCONFIGURATIONSOIC208-MILICS0VCC827DO (IO,)/HOLD (IO3)MP (IO2)CLK36GND45DI (IO)Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil(Package Code SS)4.PADCONFIGURATIONWSON8X6-MMD018CVCCICS27 CDO (IO,)/HOLD (IO3)D36CCLKP (IO2)GND045CDI (IO)Figure 1b.W25Q64BV Pad Assignments,8-pad WSON 8x6-mm(Package Code ZE)-6-
W25Q64BV - 6 - 3. PIN CONFIGURATION SOIC 208-MIL 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 8X6-MM 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1b. W25Q64BV Pad Assignments, 8-pad WSON 8x6-mm(Package Code ZE)
W25Q64BVwinbond5.PADCONFIGURATIONPDIP300-MIL018ICSVCC27DO (IO)/HOLD (IO3)MP (IO2)36CLK54GNDDI (IO0)Figure 1c. W25Q64BV Pin Assignments, 8-pin PDIP (Package Code DA)6.PINDESCRIPTIONSOIC208-MIL,PDIP300-MILANDWSON8X6-MMVOPIN NO.PIN NAMEFUNCTION1ICS1Chip Select Input2VODO (IO1)Data Output (Data Input Output 1)*13IVOWP (IO2)WriteProtectInput(DataInputOutput2)*4GNDGround5IVODI (IO0)Data Input (Data Input Output 0)*16CLK1Serial Clock Input7VOHold Input (Data Input Output 3)*2/HOLD (IO3)8VCCPowerSupply*1IO0andIO1areusedforStandardandDualSPIinstructions*2IO0-103areusedforQuadSPlinstructionsPublicationReleaseDate:July08,2010-7.RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 7 - Revision E 5. PAD CONFIGURATION PDIP 300-MIL 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) 1 2 3 4 8 7 6 5 /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1c. W25Q64BV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL AND WSON 8X6-MM PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1)*1 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2 4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0)*1 6 CLK I Serial Clock Input 7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 8 VCC Power Supply *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions
W25Q64BVwinbondPINCONFIGURATIONSOIC300-MIL7.0116/HOLD (IO.)CLK215VCCDI (IO)314N/C2N/CD13N/C4N/C>LN/C512N/CCO611N/CDN/C7ICS10GND89DO (O,)MP (IO2)DFigure1d.W25Q64BVPinAssignments,16-pin SOIC 300-mil (PackageCode SF)8.PINDESCRIPTIONSOIC300-MILVOPAD NO.PAD NAMEFUNCTION1VOHold Input (Data Input Output 3)*2/HOLD (IO3)2vCCPowerSupply3N/CNoConnect4N/CNoConnect5N/CNo Connect6N/CNoConnect7ICS-Chip Select Input8VOData Output (Data Input Output 1)*1DO (IO1)9VOWP (IO2)Write Protect Input (Data Input Output 2)*210GNDGround11N/CNo Connect12N/CNoConnect13N/CNo Connect14N/CNo Connect15VODI (IO0)Data Input (Data Input Output 0)*116CLK1Serial Clock Input*1IO0andIO1areusedforStandardandDualSPIinstructions*2IO0-1O3areusedforQuadSPIinstructions- 8 -
W25Q64BV - 8 - 7. PIN CONFIGURATION SOIC 300-MIL /HOLD (IO3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO0) N/C N/C N/C N/C GND /WP (IO ) 1 2 /HOLD (IO3) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO0) N/C N/C N/C N/C GND /WP (IO ) 1 2 Figure 1d. W25Q64BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 2 VCC Power Supply 3 N/C No Connect 4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I Chip Select Input 8 DO (IO1) I/O Data Output (Data Input Output 1)*1 9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O Data Input (Data Input Output 0)*1 16 CLK I Serial Clock Input *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions
W25Q64BVwinbond8.1PackageTypesW25Q64BVisofferedinan8-pinplastic208-milwidthSOIC(packagecodeSS)and8x6-mmWSON(packagecodeZE)asshowninfigure1a,and1b,respectively.The300-mil8-pinPDiPisanotheroptionofpackageselections(Figure1c).TheW25Q64BVisalsoofferedina16-pinplastic300-milwidthSOIC(packagecodeSF)asshowninfigure1d.Packagediagramsanddimensionsareillustratedattheendofthis datasheet.8.2 ChipSelect(/CS)The SPI Chip Select (/CS) pin enables and disables device operation. When /Cs is high the device isdeselectedand the SerialData Output(DO,or1O0,101,102,0O3)pins are athighimpedance.Whendeselected,thedevicespowerconsumptionwill beatstandbylevelsunlessan internalerase,programorstatus register cycle is inprogress.WhenIcs isbrought lowthedevicewill be selected,powerconsumptionwill increaseto activelevelsandinstructionscanbewrittentoanddatareadfromthedevice.Afterpower-up,/csmusttransitionfromhightolowbeforeanewinstructionwill beaccepted.TheICSinputmusttracktheVCCsupplylevelatpower-up(see"WriteProtection"andfigure31).Ifneededapull-upresisteron/cscanbeusedtoaccomplishthis.8.3SerialDatalnput,Outputand1Os(Dl,D0and100,101,102,103)TheW25Q64BVsupports standardSPI,Dual SPIandQuadSPIoperation.StandardSPIinstructionsusethe unidirectional Dl (input)pinto seriallywriteinstructions,addressesordatatothedeviceontherisingedgeoftheSerialClock(CLK)inputpin.StandardSPIalsousestheunidirectionalDO(output)toreaddataorstatusfromthedeviceonthefallingedgeCLK.Dual and Quad SPl instruction use the bidirectional IO pins to serially write instructions,addresses ordatatothedeviceontherisingedgeofCLKand readdataorstatusfromthedeviceonthefallingedgeofCLK.QuadSPIinstructionsrequirethenon-volatileQuadEnablebit(QE)inStatusRegister-2tobeset.WhenQE=1theWPpinbecomesIO2and/HOLDpinbecomesIO3.8.4WriteProtect(/WP)The Write Protect (WP) pin can be used to prevent the Status Register from being written. Used inconjunctionwiththeStatusRegister'sBlockProtect(SEC,TB,BP2,BP1andBPO)bitsandStatusRegisterProtect(SRP)bits,aportionortheentirememoryarraycanbehardwareprotected.TheWPpinisactivelow.WhentheQEbitofStatusRegister-2issetforQuadI/O.theWPpin(HardwareWriteProtect)functionisnotavailablesincethispinisusedforIO2.Seefigure1a,1b,1cand1dforthepinconfigurationofQuadI/Ooperation.8.5HOLD(/HOLD)The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,while /CS is iow,the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored(don'tcare).When/HOLD isbroughthigh,deviceoperationcanresume.The/HOLDfunctioncanbeuseful whenmultipledevicesaresharingthesameSPIsignals.The/HOLDpinisactivelow.WhentheQEbitof StatusRegister-2is setforQuad V/O,the/HOLD pinfunction isnotavailablesincethispinisusedforIO3.Seefigure1a-dforthepinconfigurationofQuadI/Ooperation.8.6 Serial Clock (CLK)TheSPISerialClockInput(CLK)pinprovidesthetimingforserial inputandoutputoperations.("SeeSPIOperations")PublicationReleaseDate:July08,2010- 9 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 9 - Revision E 8.1 Package Types W25Q64BV is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 8x6-mm WSON (package code ZE) as shown in figure 1a, and 1b, respectively. The 300-mil 8-pin PDIP is another option of package selections (Figure 1c). The W25Q64BV is also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1d. Package diagrams and dimensions are illustrated at the end of this datasheet. 8.2 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 31). If needed a pull-up resister on /CS can be used to accomplish this. 8.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q64BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3. 8.4 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, 1c and 1d for the pin configuration of Quad I/O operation. 8.5 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a-d for the pin configuration of Quad I/O operation. 8.6 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")
W25Q64BVwinbond9.BLOCKDIAGRAMBlockSentation7FFF0Oh7FFFFFhxxFF00hxxFFFFhBlock 127 (64KB)Sector 15 (4KB)7F0000h7F00FFhxxF000hxxFOFFhxxEF00hxxEFFFhSector 14 (4KB)xxE000hxxEOFFhxxDF0OhxxDFFFhSector 13 (4KB)xxD000hxxDOFFh.eooaoxx2F00hxx2FFFhSector 2 (4KB)Oxx20FFhx2000h40FF00h40FFFFhxx1F00hxx1FFFh0Block 64 (64KB)pueSector 1 (4KB)400000h4000FFhxx1000hxx10FFhxx0F0Ohxx0FFFh3FFF00h3FFFFFhSector 0 (4KB)Block 63 (64KB)2xx0000hxx00FFh3F0000h3F00FFhnmsnnnmsnnnmsnnnmsnnn.Write ControlWP (102) 4Logic20FF00h20FFFFhBlock 32 (64KB)200000h2000FFhStatus1FFF00h1FFFFFhRegisterBlock 31 (64KB)1F00FFh1F00004?High VoltageGenerators00FF00hOOFFFFhBlock 0 (64KB)/HOLD (IO)4000000h0000FFh Page AddressCLKLatch/CounterIBeginningEndingSPIPage AddressPage AddressICSCommand&Control LogicColumnDecodeAnd 256-Byte Page BufferDataDI (IO)DO (IO,)Byte AddressLatch/CounterFigure2.W25Q64BVSerial FlashMemoryBlockDiagram- 10 -
W25Q64BV - 10 - 9. BLOCK DIAGRAM Figure 2. W25Q64BV Serial Flash Memory Block Diagram 00FF00h 00FFFFh • Block 0 (64KB) • 000000h 0000FFh • • • 1FFF00h 1FFFFFh • Block 31 (64KB) • 1F0000h 1F00FFh 20FF00h 20FFFFh • Block 32 (64KB) • 200000h 2000FFh • • • 3FFF00h 3FFFFFh • Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh • Block 64 (64KB) • 400000h 4000FFh • • • 7FFF00h 7FFFFFh • Block 127 (64KB) • 7F0000h 7F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q64BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh • Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh • Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh • Sector 2 (4KB) • xx2000h xx20FFh • • • xxDF00h xxDFFFh • Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh • Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh • Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2) 00FF00h 00FFFFh • Block 0 (64KB) • 000000h 0000FFh • • • 1FFF00h 1FFFFFh • Block 31 (64KB) • 1F0000h 1F00FFh 20FF00h 20FFFFh • Block 32 (64KB) • 200000h 2000FFh • • • 3FFF00h 3FFFFFh • Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh • Block 64 (64KB) • 400000h 4000FFh • • • 7FFF00h 7FFFFFh • Block 127 (64KB) • 7F0000h 7F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q64BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh • Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh • Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh • Sector 2 (4KB) • xx2000h xx20FFh • • • xxDF00h xxDFFFh • Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh • Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh • Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2)