W25Q64BVwinbond11.1.8 StatusRegisterMemoryProtectionSTATUS REGISTER(1)W25Q64BV(64M-BIT)MEMORYPROTECTIONSECTBBP2BP1BPOBLOCK(S)ADDRESSESDENSITYPORTIONxx000NONENONENONENONE00001126&127128KBUpper 1/647E0000h-7FFFFFh00010Upper1/32124~127256KB7C0000h-7FFFFFh10001120~127780000h-7FFFFFh512KBUpper1/1600100112~1271MBUpper 1/8700000h-7FFFFFh0010196 ~ 1272MBUpper1/4600000h-7FFFFFh0101064~1274MBUpper 1/2400000h1-7FFFFFh110000&1128KBLower 1/64000000h1-01FFFFh010100~3256KBLower1/32000000h-03FFFFh010110~7512KBLower1/16000000h-07FFFFh011001MB0 ~ 15000000h-0FFFFFhLower1/8010110~312MB000000h-1FFFFFhLower 1/4011100~634MB000000h-3FFFFFhLower 1/2xx111ALL0 ~ 1278MB000000h-7FFFFFh100101274KBTop Block7FF000h-7FFFFFh100101278KB7FE000h-7FFFFFhTop Block1011012716KBTop Block7FC00Oh-7FFFFFh1010x12732KB7F8000h1-7FFFFFhTop Block1101004KB000000h1-000FFFhBottomBlock110100001FFFh8KB000000h-BottomBlock110110000000h003FFFh16KBBottomBlock-1x1100-007FFFh32KB000000hBottomBlockNote:1. x= don't care- 16 -
W25Q64BV - 16 - 11.1.8 Status Register Memory Protection STATUS REGISTER(1) W25Q64BV (64M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 126 & 127 7E0000h – 7FFFFFh 128KB Upper 1/64 0 0 0 1 0 124 ~ 127 7C0000h – 7FFFFFh 256KB Upper 1/32 0 0 0 1 1 120 ~ 127 780000h – 7FFFFFh 512KB Upper 1/16 0 0 1 0 0 112 ~ 127 700000h – 7FFFFFh 1MB Upper 1/8 0 0 1 0 1 96 ~ 127 600000h – 7FFFFFh 2MB Upper 1/4 0 0 1 1 0 64 ~ 127 400000h – 7FFFFFh 4MB Upper 1/2 0 1 0 0 1 0 & 1 000000h – 01FFFFh 128KB Lower 1/64 0 1 0 1 0 0 ~ 3 000000h – 03FFFFh 256KB Lower 1/32 0 1 0 1 1 0 ~ 7 000000h – 07FFFFh 512KB Lower 1/16 0 1 1 0 0 0 ~ 15 000000h – 0FFFFFh 1MB Lower 1/8 0 1 1 0 1 0 ~ 31 000000h – 1FFFFFh 2MB Lower 1/4 0 1 1 1 0 0 ~ 63 000000h – 3FFFFFh 4MB Lower 1/2 X X 1 1 1 0 ~ 127 000000h – 7FFFFFh 8MB ALL 1 0 0 0 1 127 7FF000h – 7FFFFFh 4KB Top Block 1 0 0 1 0 127 7FE000h – 7FFFFFh 8KB Top Block 1 0 0 1 1 127 7FC000h – 7FFFFFh 16KB Top Block 1 0 1 0 X 127 7F8000h – 7FFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block Note: 1. x = don’t care
W25Q64BVwinbond11.2INSTRUCTIONSTheinstructionsetoftheW25Q64BVconsistsoftwentysevenbasicinstructionsthatarefullycontrolledthroughtheSPlbus (seeInstructionSettable).Instructionsare initiatedwiththe fallingedgeof ChipSelect (CS).The first byte of data clocked into the DI input provides the instruction code.Data on the DIinputissampledontherisingedgeofclockwithmostsignificantbit(MSB)first.Instructionsvaryinlengthfromasinglebytetoseveralbytesandmaybefollowedbyaddressbytes,databytes, dummy bytes (don't care),and in some cases,a combination. Instructions are completed with therising edge of edge /cs.Clock relative timing diagrams for each instruction are included in figures 4through3o.All read instructions canbe completedafter anyclocked bit.However,all instructionsthatWriteProgramorErasemustcompleteonabyteboundary(/CSdrivenhighafterafull8-bitshavebeenclocked)otherwise the instructionwill be terminated.This feature further protects thedevice frominadvertent writes. Additionally,while the memory is being programmed or erased, or when the StatusRegister is being written,all instructions exceptfor Read Status Register will be ignored until theprogramorerasecyclehascompleted11.2.1ManufacturerandDeviceldentificationMANUFACTURERID(M7-MO)EFhWinbond Serial Flash(ID15-IDO)DeviceID(ID7-ID0)9FhInstructionABh, 90hW25Q64BV16h4017hPublicationReleaseDate:July08,2010- 17 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 17 - Revision E 11.2 INSTRUCTIONS The instruction set of the W25Q64BV consists of twenty seven basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4 through 30. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 11.2.1 Manufacturer and Device Identification MANUFACTURER ID (M7-M0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h 9Fh W25Q64BV 16h 4017h
W25Q64BVwinbond11.2.2 Instruction Set Table 1 ()INSTRUCTIONBYTE1BYTE2BYTE3BYTE 4BYTE5BYTE6NAME(CODE)Write Enable06h04hWrite Disable(S7-S0) (2)05hRead Status Register-1(S15-S8 (2)35hRead Status Register-201h(S7-SO)(S15-S8)WriteStatus Register02hA23-A16A15-A8A7-A0(D7-DO)Page Program(D7-D,. . .)32hA23-A16A15-A8A7-A0Quad PageProgramD8hA23-A16A15-A8A7-A0Block Erase (64KB)52hA15-A8A7-A0Block Erase (32KB)A23-A1620hA23-A16A15-A8A7-A0Sector Erase (4KB)Chip EraseC7h/60h75hErase Suspend7AhEraseResumeB9hPower-downA3hdummyHigh Performance Modedummy dummyContinuous Read ModeFFhFFhReset (4)Release Powerdown or(ID7-IDO) (5)ABhdummydummydummyHPM / Device IDManufacturer/90h00hdummydummy(MF7-MF0)(ID7-IDO)Device ID(6)Read Unique ID()4Bhdummydummydummydummy(ID63-IDO)(MF7-MF0)(ID15-ID8)(ID7-IDO)JEDECID9FhManufacturerMemory TypeCapacityNotes:1.Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis“0" indicate data being readfromthedeviceontheDOpin2.The StatusRegister contentswill repeat continuouslyuntil/CS terminates the instruction.3.QuadPageProgramInputDataIOO = (D4. DO....)IO1 - (D5., D1...)IO2 = (D6, D2,.....IO3 =(D7, D3,....4.Thisinstruction isrecommendedwhenusing theDualorQuad"ContinuousReadMode"feature.Seesection11.2.29formoreinformation.5.TheDeviceIDwill repeatcontinuouslyuntil/CSterminatesthe instruction.6.See Manufacturerand Device Identification tablefor Device ID information.7.Thisfeature is availableupon special order.Please contact Winbond fordetails.-18 -
W25Q64BV - 18 - 11.2.2 Instruction Set Table 1 (1) INSTRUCTION NAME BYTE 1 (CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Write Disable 04h Read Status Register-1 05h (S7–S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7–S0) (S15-S8) Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, .)(3) Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0 Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Chip Erase C7h/60h Erase Suspend 75h Erase Resume 7Ah Power-down B9h High Performance Mode A3h dummy dummy dummy Continuous Read Mode Reset (4) FFh FFh Release Power down or HPM / Device ID ABh dummy dummy dummy (ID7-ID0) (5) Manufacturer/ Device ID(6) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) Read Unique ID(7) 4Bh dummy dummy dummy dummy (ID63-ID0) JEDEC ID 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. Quad Page Program Input Data IO0 = (D4, D0, .) IO1 = (D5, D1, .) IO2 = (D6, D2, .) IO3 = (D7, D3, .) 4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See section 11.2.29 for more information. 5. The Device ID will repeat continuously until /CS terminates the instruction. 6. See Manufacturer and Device Identification table for Device ID information. 7. This feature is available upon special order. Please contact Winbond for details
W25Q64BVwinbond11.2.3 Instruction SetTable2(Read Instructions)INSTRUCTIONBYTE1BYTE2BYTE3BYTE4BYTE5BYTE6NAME(CODE)Read Data03hA23-A16A15-A8(D7-DO)A7-A0Fast ReadOBhA23-A16A15-A8A7-A0dummy(D7-DO)(7-D. .))Fast Read Dual Output3BhA23-A16A15-A8A7-A0dummy(D7-DO, ..)()A23-A8(2)A7-A0, M7-Mo(2)BBhFastRead Dual I/O(D7-D,.. .3)6BhA23-A16A15-A8A7-A0Fast ReadQuadOutputdummyA23-A0, M7-Mo(4)(XX,X,x, D7-DO. .)(5)(D7-DO, .. (3)EBhFastReadQuadVOOctal Word ReadA23-A0, M7-Mo(4)(D7-D0, .)(3)E3hQuad Vo(6)Notes:1.Dual Output data1O0 = (D6, D4, D2, DO)IO1 = (D7, D5, D3, D1)2. Dual Input AddressIO00=A22,A20,A18,A16,A14,A12,A10,A8A6.A4.A2.A0,M6.M4,M2.M0IO1 = A23, A21, A19, A17,A15, A13, A11, A9 A7,A5,A3,A1,M7,M5,M3,M13.QuadOutputDataIOO = (D4, DO,...)IO1 = (D5, D1,....)IO2 = (D6, D2,...)I03 = (D7,D3,....)4.Quad Input AddressIO0=A20,A16,A12,A8,A4,A0,M4,M0IO1 =A21, A17,A13, A9,A5,A1,M5,M1I02=A22,A18,A14,A10.A6,A2,M6,M2IO3 =A23,A19,A15,A11.A7,A3, M7,M35.FastReadQuadVOData100 = (X, X, x, x, D4, DO,, .*..)IO1 = (x, X, x, x, D5, D1,, ....IO2 = (x, x, x, ×, D6, D2, ....)IO3 = (x x, x, x, D7, D3, ...)6. The lowest 4 address bits must be 0. (A0, A1,A2, A3 =0)PublicationReleaseDate:July08.2010- 19 -RevisionE
W25Q64BV Publication Release Date: July 08, 2010 - 19 - Revision E 11.2.3 Instruction Set Table 2 (Read Instructions) INSTRUCTION NAME BYTE 1 (CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, .)(1) Fast Read Dual I/O BBh A23-A8(2) A7-A0, M7-M0(2) (D7-D0, .)(1) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, .)(3) Fast Read Quad I/O EBh A23-A0, M7-M0(4) (x,x,x,x, D7-D0, .)(5) (D7-D0, .)(3) Octal Word Read Quad I/O(6) E3h A23-A0, M7-M0(4) (D7-D0, .)(3) Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, .) IO1 = (D5, D1, .) IO2 = (D6, D2, .) IO3 = (D7, D3, .) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, .) IO1 = (x, x, x, x, D5, D1, .) IO2 = (x, x, x, x, D6, D2, .) IO3 = (x, x, x, x, D7, D3, .) 6. The lowest 4 address bits must be 0. ( A0, A1, A2, A3 = 0 )
W25064BVwinbond11.2.4WriteEnable(06h)TheWriteEnableinstruction(Figure4)setstheWriteEnableLatch(WEL)bit intheStatusRegistertoa1.TheWELbitmustbe setpriorto everyPageProgram,SectorErase,Block Erase,ChipEraseandWriteStatusRegisterinstruction.TheWriteEnableinstructionisenteredbydriving/CSlow,shiftingtheinstruction code "o6h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /Cs high./CSMode 3Mode 3Mode0ModeoCLKInstruction (06h)DXXXXXXXXXXHighImpedanceDOFigure4.WriteEnableInstructionSequenceDiagram11.2.5WriteDisable(04h)The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL)bit in the Status Registertoa0.TheWriteDisableinstructionisenteredbydrivingICSlow,shiftingtheinstructioncode“04hintotheDIpinandthendrivingICshigh.NotethattheWEL bit isautomaticallyresetafterPower-upanduponcompletionoftheWriteStatusRegister,PageProgram,SectorErase,BlockEraseandChip Eraseinstructions./CSMode36Mode3Mode oMode 0CLKInstruction(04h)XXXXDIXXXXXXHighImpedanceDOFigure5.Write Disable Instruction SequenceDiagram- 20 -
W25Q64BV - 20 - 11.2.4 Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Sequence Diagram 11.2.5 Write Disable (04h) The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 5. Write Disable Instruction Sequence Diagram